• 한국진공학회:학술대회논문집
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• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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• pp.142.2-142.2
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• 2015

Plasma etch endpoint detection (EPD) of SiO2 and PR layer is demonstrated by plasma impedance monitoring in this work. Plasma etching process is the core process for making fine pattern devices in semiconductor fabrication, and the etching endpoint detection is one of the essential FDC (Fault Detection and Classification) for yield management and mass production. In general, Optical emission spectrocopy (OES) has been used to detect endpoint because OES can be a simple, non-invasive and real-time plasma monitoring tool. In OES, the trend of a few sensitive wavelengths is traced. However, in case of small-open area etch endpoint detection (ex. contact etch), it is at the boundary of the detection limit because of weak signal intensities of reaction reactants and products. Furthemore, the various materials covering the wafer such as photoresist (PR), dielectric materials, and metals make the analysis of OES signals complicated. In this study, full spectra of optical emission signals were collected and the data were analyzed by a data-mining approach, modified K-means cluster analysis. The K-means cluster analysis is modified suitably to analyze a thousand of wavelength variables from OES. This technique can improve the sensitivity of EPD for small area oxide layer etching processes: about 1.0 % oxide area. This technique is expected to be applied to various plasma monitoring applications including fault detections as well as EPD.

• Transactions on Electrical and Electronic Materials
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• 제12권2호
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• pp.60-63
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• 2011

We investigated the etching characteristics of zinc oxide (ZnO) and the effect of additive gases in a $Cl_2$-based inductively coupled plasma. The inert gases were argon, nitrogen, and helium. The maximum etch rates were 44.3, 39.9, and 37.9 nm/min for $Cl_2$(75%)/Ar(25%), $Cl_2$(50%)/$N_2$(50%), and $Cl_2$(75%)/He(25%) gas mixtures, 600 W radiofrequency power, 150 W bias power, and 2 Pa process pressure. We obtained the maximum etch rate by a combination of chemical reaction and physical bombardment. A volatile compound of Zn-Cl. achieved the chemical reaction on the surface of the ZnO thin films. The physical etching was performed by inert gas ion bombardment that broke the Zn-O bonds. The highly oriented (002) peak was determined on samples, and the (013) peak of $Zn_2SiO_4$ was observed in the ZnO thin film sample based on x-ray diffraction spectroscopy patterns. In addition, the sample of $Cl_2$/He chemistry showed a high full-width at half-maximum value. The root-mean-square roughness of ZnO thin films decreased to 1.33 nm from 5.88 nm at $Cl_2$(50%)/$N_2$(50%) plasma chemistry.

• Journal of the Optical Society of Korea
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• 제18권5호
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• pp.569-573
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• 2014

We demonstrate a low-cost, superbly efficient way of etching for the nano-, and micro-sized pyramid patterns on (100)-oriented Si wafer surfaces for use as a patterned master. We show a way of producing functional optical films for the viewing angle direction brightness-enhancement of Lambertian LED (light emitting diode)/OLED (organic light emitting diode) planar lighting applications. An optimally formulated KOH (Potassium hydroxide) wet etching process enabled random-positioned, and random size-distributed (within a certain size range) pyramid patterns to be developed over the entire (100) silicon wafer substrates up to 8" and a simple replication process of master patterns onto the PC (poly-carbonate) and PMMA (poly-methyl methacrylate) films were performed. Haze ratio values were measured for several film samples exhibiting excellent values over 90% suitable for LED/OLED lighting purposes. Brightness was also improved by 13~14% toward the viewing angle direction. Computational simulations using LightTools$^{TM}$ were also carried out and turned out to be in strong agreement with experimental data. Finally, we could check the feasibility of fabricating low-cost, large area, high performance optical films for commercialization.

• 한국전기전자재료학회논문지
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• 제18권5호
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• pp.389-395
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• 2005

The etching technology of the high aspect ratio contact(HARC) is necessary at the critical contact processes of semiconductor devices. Etching the $SiO_{2}$ contact hole with the sub-micron design rule in manufacturing VLSI devices, the unexpected phenomenon of 'profile tilting' or 'bottom distortion' is often observed. This makes a short circuit between neighboring contact holes, which causes to drop seriously the device yield. As the aspect ratio of contact holes increases, the high C/F ratio gases, $C_{4}F_{6}$, $C_{4}F_{8}$ and $C_{5}F_{8}$, become widely used in order to minimize the mask layer loss during the etching process. These gases provide abundant fluorocarbon polymer as well as high selectivity to the mask layer, and the polymer with high sticking yield accumulates at the top-wall of the contact hole. During the etch process, many electrons are accumulated around the asymmetric hole mouth to distort the electric field, and this distorts the ion trajectory arriving at the hole bottom. These ions with the distorted trajectory induce the deformation of the hole bottom, which is called 'profile tilting' or 'bottom distortion'. To prevent this phenomenon, three methods are suggested here. 1) Using lower C/F ratio gases, $CF_{4}$ or $C_{3}F_{8}$, the amount of the Polymer at the hole mouth is reduced to minimize the asymmetry of the hole top. 2) The number of the neighboring holes with equal distance is maximized to get the more symmetry of the oxygen distribution around the hole. 3) The dual frequency plasma source is used to release the excessive charge build-up at the hole mouth. From the suggested methods, we have obtained the nearly circular hole bottom, which Implies that the ion trajectory Incident on the hole bottom is symmetry.

• 한국재료학회지
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• 제7권2호
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• pp.102-106
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• 1997

박막형 접촉연소식을 포함한 마이크로 가스센서에서 membrane은 Si식각시 식각정지용으로서 또 센서 소자를 지지하는 층으로서 응력이 없어야 하며 이는 응력이 membrane파괴의 주 원인으로 작용하기 때문이다. 이에 따라 본 연구에서는 증착조건이 low pressure chemical vapor deposition(LPCVD)법과 sputtering법으로 제작된 $SiN_{x}$과 $SiN_{x}/SiO_{x}/(NON)$막의 응력고 굴절율 변화에 미치는 효과에 대한 실험을 행하였다. LPCVD의 경우 단일막인 $SiN_{x}$의 압축응력 및 굴절율을 나타내었다. Sputtering의 경우 $SiN_{x}$는 공정압력이 1mtorr에서 30torr까지 증가할수록 인가전력밀도가 $2.74W/cm^2$에서 $1.10W/cm^2$으로 감소할수록 응력값은 압축에서 인장으로 전환되었으며 본 실험에서 응력이 가장 낮게 나온 시편의경우 압축응력으로 $1.2{\times}10^{9}dyne/cm^2$가 공정압력 10mtorr, 인가전력밀도 $1.37W/cm^2$에서 얻어졌다. 굴절율은 공정압력이 1motorr에서 30motorr까지 증가할수혹 인가전력밀도가 $2.74W/cm^2$에서 $1.10W/cm^2$으로 감소할수록 감소하여 2.05에서 1.89의 변화를 보였다. LPCVD와 sputtering으로 증착된 막들은 모두 온도가 증가함에 따라 응력이 감소하였으며 온도감소시 소성적인 특성을 나타내었다.

• 공업화학
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• 제26권5호
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• pp.543-548
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• 2015

리튬이온 전지용 음극소재의 용량 및 사이클 성능을 향상시키기 위해서 Si/C/CNF 합성물의 특성이 조사되었다. 제조과정으로는 SBA-15를 합성하고 볼밀링을 이용한 마그네슘환원을 통해 Si/MgO를 얻은 다음, Phenolic resin과 CNF를 이용해 탄화과정을 거쳐 최종적으로 산처리하여 Si/C/CNF 활물질을 합성하였다. 합성된 Si/C/CNF는 BET, XRD, FE-SEM 그리고 TGA를 이용하여 분석하였다. $50^{\circ}C{\sim}70^{\circ}C$까지 온도에 따라 SBA-15를 합성한 결과 $60^{\circ}C$에서 가장 큰 비표면적을 갖는 결과를 얻었다. 또한 LiPF6 (EC : DMC : EMC = 1 : 1 : 1 vol%) 전해질을 사용하여, 충방전, 사이클, CV와 임피던스 등과 같은 전기화학적 테스트를 수행하여 Si/C/CNF 전극의 이차전지 음극활물질로서 성능을 조사하였다. Si/C/CNF (Si : CNF = 97 : 3 중량비)를 이용한 전지의 용량은 1,947 mAh/g으로 다른 합성물보다 우수한 결과를 보였다. CNF 첨가량이 3 wt%에서 11 wt%로 증가함에 따라 용량 보존율이 84~77%로 안정성이 감소되었다. Si/C/CNF 합성소재 전극이 이차전지의 사이클 성능과 전기전도도를 개선할 수 있다는 것을 알 수 있었다.

• ETRI Journal
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• 제35권3호
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• pp.425-430
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• 2013

In this paper, we propose a triple-gate trench power MOSFET (TGRMOS) that is made through a modified RESURF stepped oxide (RSO) process, that is, the nitride_RSO process. The electrical characteristics of TGRMOSs, such as the blocking voltage ($BV_{DS}$) and on-state current ($I_{D,MAX}$), are strongly dependent on the gate configuration and its bias condition. In the nitride_RSO process, the thick single insulation layer ($SiO_2$) of a conventional RSO power MOSFET is changed to a multilayered insulator ($SiO_2/SiN_x/TEOS$). The inserted $SiN_x$ layer can create the selective etching of the TEOS layer between the gate oxide and poly-Si layers. After additional oxidation and the poly-Si filling processes, the gates are automatically separated into three parts. Moreover, to confirm the variation in the electrical properties of TGRMOSs, such as $BV_{DS}$ and $I_{D,MAX}$, simulation studies are performed on the function of the gate configurations and their bias conditions. $BV_{DS}$ and $I_{D,MAX}$ are controlled from 87 V to 152 V and from 0.14 mA to 0.24 mA at a 15-V gate voltage. This $I_{D,MAX}$ variation indicates the specific on-resistance modulation.

• Journal of Welding and Joining
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• 제24권2호
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• pp.64-70
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• 2006

The 3-dimensional (3D) chip stacking technology is a leading technology to realize a high density and high performance system in package (SiP). There are several kinds of methods for chip stacking, but the stacking and interconnection through Cu filled through-hole via is considered to be one of the most advanced stacking technologies. Therefore, we studied the optimum process of through-hole via formation and Cu filling process for Si wafer stacking. Through-hole via was formed with DRIE (Deep Reactive ion Etching) and Cu filling was realized with the electroplating method. The optimized conditions for the via formation were RE coil power of 200 W, etch/passivation cycle time of 6.5 : 6 s and SF6 : C4F8 gas flow rate of 260 : 100 sccm. The reverse pulsed current of 1.5 A/dm2 was the most favorable condition for the Cu electroplating in the via. The Cu filled Si wafer was chemically and mechanically polished (CMP) for the following flip chip bumping technology.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2013년도 춘계학술대회
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• pp.772-775
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• 2013

사파이어 위에 MOCVD로 성장한 p-GaN 위에 PECVD로 $SiO_2$ $2500{\AA}$을 증착하여 열처리실험을 진행하였다. 열처리 후 $SiO_2$ 보호막을 식각하여, 정공 농도를 측정하고, 이를 열처리 전의 데이터 값과 비교, 분석하였다. 또한, 분위기가스인 $N_2$와 $O_2$의 비율, 급속 열처리 온도 ($650^{\circ}C$와 $750^{\circ}C$) 및 시간(1분~15분)에 따른 정공의 이동도와 농도의 변화를 측정하였으며, 상온 및 저온 PL 측정을 통하여 후열처리에 따른 시료의 광학적, 구조적 성질을 조사하였다.

• Korean Chemical Engineering Research
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• 제54권4호
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• pp.459-464
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• 2016

본 연구에서는 리튬이온 전지용 실리콘 음극소재의 사이클 안정성 및 율속 특성 향상을 위해 다공성 실리콘/탄소 복합소재의 전기화학적 특성을 조사하였다. 나노 실리카 제조는 스토버 방법을 사용하고 교반 속도, 교반 온도 및 $NH_3$/TEOS 비율을 조절 하여 100~500 nm 크기의 구형 실리카를 합성하였다. 구형 나노 실리카의 마그네슘 열환원과 산처리 과정을 통해 다공성 실리콘을 얻고, 제조된 다공성 실리콘에 Phenolic resin을 탄소전구체로 사용하여 최종적으로 다공성 실리콘/탄소 활물질을 합성하였다. 또한 $LiPF_6$ (EC:DMC:EMC=1:1:1 vol%) 전해액에서 다공성 실리콘/탄소 음극소재의 충 방전, 순환전압 전류, 임피던스 테스트 등의 전기화학적 특성을 조사 하였다. 다공성 실리콘/탄소 복합소재의 음극활물질로서 코인 전지의 성능을 조사한 결과 초기용량 및 40사이클 용량 보존율은 각각 2,006 mAh/g, 55.4%를 나타내었다.