• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.153-156
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• 2009

The interferometric fiber optic gyroscopes (FOGs) are well known as sensors of rotation, which are based on Sagnac effect, and have been under development for a number of years to meet a wide range of performance requirements. This paper describes the development of open-loop FOG and digital signal processing techniques implemented on FPGA. Our primary goal was to obtain intermediate accuracy (pointing grade) with a good bias stability ($0.22^{\circ}/hr$) and scale factor stability, extremely low angle random walk ($0.07^{\circ}/\sqrt{hr}$) and significant cost savings by using a single mode fiber. A secondary goal is to design all digital FOG signal processing algorithms with which the SNR at the digital demodulator output is enhanced substantially due to processing gain. The CIC type of decimation block only requires adders and shift registers, low cost processors which has low computing power still can used in this all digital FOG processor.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.13 no.5
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• pp.137-145
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• 2003

Nowadays, people can communicate with each other on any time at my place by development of wireless communications. But, the openness of mobile communications Poses serious security threats and the security is necessary on mobile communications to support the secure communication channel. The most commonly method is stream cipher for mobile communications. Generally, this stream cipher is implemented by LFSR(Linear Feedback Shift Register). On this paper proposes the modified mechanism of the S box is usually used in block cipher to advance security og the stream cipher and this mechanism is the modified three one in consideration og the randomness. Generally, S box that is function with nonlinear property makes data more strong by attack. The randomness test of the proposed algorithm is used Ent Pseudorandom Number Sequence Test Program and by the test result it proves that it has better randomness and serial correlation value than the based stream cipher on respective test.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1420-1421
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• 2011

비정질 IGZO 박막 트랜지스터에 포지티브 직류/교류 게이트 바이어스를 인가하여 신뢰성을 분석하고 비정질 IGZO 박막 트랜지스터의 신뢰성을 고려한 시프트 레지스터 회로를 설계하였다. 비정질 IGZO 박막 트랜지스터의 문턱전압은 바이어스 스트레스가 인가되었을 때 양의 방향으로 이동하였고, 전류가 감소하였다. 또한 문턱전압은 직류 바이어스 스트레스가 인가되었을 때 교류 바이어스 스트레스가 인가 되었을 때 보다 더 양의 방향으로 이동하였다. 총 8개의 박막 트랜지스터로 구성된 일반적인 시프트 레지스터 회로에서는 특정 박막 트랜지스터에 직류 바이어스 스트레스가 걸리기 때문에 비정질 IGZO 박막 트랜지스터를 이용하여 구동할 때 회로 오동작을 유발할 수 있다. 비정질 IGZO 박막 트랜지스터의 신뢰성 결과를 고려하여 총 9개의 박막 트랜지스터로 구성된 교류 동작하는 시프트 레지스터 회로를 설계하였다. 모든 소자에 직류 바이어스 스트레스가 걸리지 않도록 회로를 설계하였으며, 추가된 트랜지스터의 채널 너비가 매우 작기 때문에 트랜지스터가 하나 추가되어도 회로가 차지하는 면적에는 거의 변화가 없다. 바이어스 스트레스에 따른 소자 열화를 고려하여 시뮬레이션을 해 본 결과 일반적인 회로에서는 회로 오동작이 관측된 반면, 제안한 회로에서는 문제없이 동작하는 것을 확인하였다.

• Journal of Korea Multimedia Society
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• v.14 no.6
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• pp.759-765
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• 2011

In this paper, we proposed fast stream cipher MS64 for use mobile that it is secure, fast, and easy to implement software. The proposed algorithm use the fast operating 213-bit arithmetic shift register(ASR) to generate a binary sequence and produce 64-bit stream cipher by using simple logical operation in non linear transform. MS64 supports 128-bit key in encryption algorithm and satisfy with the safety requirement in modern encryption algorithm. In simulation result shows that MS64 is faster than a 32-bit stream cipher SSC2 in the speed of operation with small usage of memory thus MS64 can be used for mobile devices with fast ciphering.

• THE INTERNATIONAL COMMERCE & LAW REVIEW
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• v.67
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• pp.49-68
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• 2015

In recent years in China, corresponding to a shift in consumption pattern from household basics to greater expenditure on quality of life, new franchising opportunities arise. Although the franchising prospect in China is promising, Korean companies aiming at franchising into China need to be aware of the legal framework for commercial franchise in China as this will have direct impact on their business expansion. Where franchising activities involve trade mark licence, Chinese Franchise Regulations require such trade mark licence agreement to be regulated in accordance with the relevant provisions of the Chinese Trademark Law. Furthermore where one party fails to perform his obligation and it impacts purpose of the contract seriously, the other party could avoid the contract in accordance with the relevant provisions of the Chinese Contract Law. To launch franchising business successfully in China, Korean companies do market research sufficiently before they may commence franchise business. Korean franchisor must register with local authorities in China by own name, and make Chinese partner take charge of management of the distribution network and invitation of franchisee partners.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.4
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• pp.34-41
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• 2003

A new technique for detecting parametric faults in mixed signal circuits is proposed Pseudo-random sequence from linear feedback shift register(LFSR) is fed to circuit-under-test (CUT) as stimulus and wavelets are used to compact the transient response under this stimulus into a small number of signature. Wavelet based scheme decomposes the transient response into a number of signal in different frequency bands. Each decomposed signal is compacted into a signature using digital integrator. The digital pulses from LFSR, owing to its pseudo-randomness property, are almost uniform in frequency domain, which generates multi-frequency response when passed through CUT. The effectiveness of this technique is demonstrated in our experimental results.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.1
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• pp.79-86
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• 1996

In this paper we propose an architecture for VLC(Variable Length Coder) and VLD(Variable Length Decoder) which is simple with respect to implementation point and efficient in memory. We implemented encoding and decoding circuit where we need only 7-bit address memory space for 114 MPEG1 DCT coefficients and employed minimal number of flip-flops and logics for an architecture to integrate a shift register for serial-to-parallel or parallel-to-serial conversion of the data in code mapping ROM. We obtained 50Mbps operating speed in both encoding and decoding process as the result of simulation using 0.80.8${\mu}m$ CMOS standard cells.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1959-1960
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• 2008

The Logic Built In Self Test (LBIST) technique is substantially applied in chip design in most many semiconductor company in despite of unavoidable overhead like an increase in dimension and time delay occurred as it used. Currently common LBIST software uses the MISR (Multiple Input Shift Register) However, it has many considerations like defining the X-value (Unknown Value), length and number of Scan Chain, Scan Chain and so on for analysis of result occurred in the process. So, to solve these problems, common LBIST software provides the solution method automated. Nevertheless, these problems haven't been solved automatically by Tri-state Bus in logic circuit yet. This paper studies the algorithm that it also suggest algorithm that reduce additional circuits and time delay as matching of pattern about 2-type circuits which are CUT(circuit Under Test) and additional circuits so that the designer can detect the wrong location in CUT: Circuit Under Test.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.4
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• pp.243-250
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• 2005

Test methodology is diversity by devices and the number of test pattern is tremendous because the digital circuit includes TTL and CMOS family ICs as well as high density devices such as ROM and RAM. Accordingly, the quick and effective test strategy is required to enhance the test productivity. This paper proposes the test strategy which is able to be applied efficiently to the diversity devices on the digital circuit board by analyzing the structure and characteristic of the digital device. Especially, this test strategy detects the faulted digital device or the faulted digital circuit on the digital board using SSA(Serial Signature Analysis) technique based on the polynomial division theory The SSA technique identifies the faults by comparing the reminder from good device with reminder from the tested device. At this time, the reminder is obtained by enforcing the data stream obtained from output pins of the tested device on the LFSR(Linear Feedback Shift Register) representing the characteristic equation. Also, the method to obtain the optimal signature analysis circuit is explained by furnishing the short bit input streams to the long bit input streams to the LFSR having 8, 12, 16, 20bit input/output pins and by analyzing the occurring probability of error which is impossible to detect. Finally, the effectiveness of the proposed test strategy is verified by simulating the stuck at 1 errors or stuck at 0 errors for several devices on typical 8051 digital board.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.470-480
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• 2016

The reversal of a silicon chip to find out its security structure is common and possible at the present time. Thanks to reversing, it is possible to use a probing attack to obtain useful information such as personal information or a cryptographic key. For this reason, security-related blocks such as DES (Data Encryption Standard), AES (Advanced Encryption Standard), and RSA (Rivest Shamir Adleman) engines should be located in the lower layer of the chip to guard against a probing attack; in this regard, the addition of a silicon-surface-protection layer onto the chip surface is a crucial protective measure. But, for manufacturers, the implementation of an additional silicon layer is burdensome, because the addition of just one layer to a chip significantly increases the overall production cost; furthermore, the chip size is increased due to the bulk of the secure logic part and routing area of the silicon protection layer. To resolve this issue, this paper proposes a practical silicon-surface-protection method using a metal layer that increases the security level of the chip while minimizing its size and cost. The proposed method uses a shift register for the alternation and variation of the metal-layer data, and the inter-connection area is removed to minimize the size and cost of the chip in a more extensive manner than related methods.