• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.82-85
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• 1998

Because ATM was originally designed for the optical fiber environment with bit error rate(BER) of 10-11, it is difficult to maintain ATM cell extraction capability in wireless environment where BER ranges from 10-6 to 10-3. Therefore, it must be proposed the algorithm of ATM cell extraction in wereless environment. In this paper, the frame structure and synchronization algorithm satisfyling the above condition are explained, and the new ASIC implementation method of this algorithm is proposed. The known method using shift register needs so many gates that it is not suitable for ASIC implementation. But in the proposed method, a considerable reduction in gate count can be achieved by using random access memory.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.717-720
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• 1998

In this paper, we propose a VLSI architecture for implementing a crecently proposed fast block matching algorithm, which is called the HSBMA3S. The proposed architecture consists of a systolic array based basic unit and two shift register arrays. And it covers a search range of -32 ~+31. By using a basic unit repeatedly, we can redcue the number of gates. To implement the basic unit, we can select one among various conventional systolic arrays by trading-off between speed and hardware cost. In this paper, the architecture for the basic unit is selected so that the hardware cost can be minimized. The proposed architecture is fast enough for low bit-rate applications (frame size of 352x288, 30 frames/sec) and can be implemented by less than 20,000 gates. Moreover, by simply modifying the basic unit, the architecture can be used for the higher bit-rate application of the frame size of 720*480 and 30 frames/sec.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.1305-1308
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• 2008

In this study, we redesigned the reliable integrated on-panel display gate driver that was equipped with dual pull-down as well as controlled discharge-path structure to reduce the high voltage stress effect and realized with TSMC 0.35 um CMOS-based technology before. An improved discharge path and a low noise design are proposed for our new a-Si TFT process implementation. Our novel reliable gate driver design can make each cell of shift register to be insensitive to the coupling noise of that stage.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.605-606
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• 2008

The distance detection system receives stereo video input through 2 CCD cameras. Using a decoder, the image is changed to the YCbCr4:2:2 format and only the Y signal is saved in the 4*256*8bit shift register of the Dual-Port SRAM. As a result of the matching procedure, the Depth value, which is the distance information, is saved in SRAM, and the Depth Map is made and output to the TFT-LCD screen.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.583-584
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• 2008

This paper presents a low-power and high-speed pulsed flip-flop based on dual-precharging and conditional discharging. The dual-precharging operation minimizes the parasitic capacitance of each precharge node, resulting in high-speed operation. The conditional-discharging operation minimizes the redundant transitions of precharge nodes, resulting in low-power operation. Linear feedback shift register (LFSR) designed in a $0.18{\mu}m$ CMOS technology using the proposed flip-flop achieves 32% power reduction as compared to conventional design.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1988년도 한국자동제어학술회의논문집(국제학술편); 한국전력공사연수원, 서울; 21-22 Oct. 1988
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• pp.943-946
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• 1988

A simple method is proposed for determining the frequency response function G(j.omega.) of a system using a pair of characteristic M-sequences (maximum length linear feed back shift register sequence). When a characteristic M-sequence is sampled with q$_{1}$ and q$_{2}$ both of which are coprime with N, where N is the period of the M-sequence, the obtained pair of sequences have conjugate complex frequency spectrum. Making use of this fact, two charcteristic M-sequences having conjugate complex frequency spectrum are applied to a system to be measured. Since the magnitude of spectrium of M-sequence is known, the gain of G(j.omega.) is directly obtained from the Fourier transform of the system output. The phase of G(j.omega.) is obtained simply by taking the average of the two phases of output spectrum.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.935-938
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• 1999

메모리 테스트는 Built-In Self Test(BIST)와 같이 메모리에 내장된 회로를 통하여 자체 점검하는 방법과 테스터를 통하여 생성된 패턴을 주입하는 방법이 있다. 테스트 패턴 생성방법으로는 각각의 고장모델에 대한 테스트 패턴을 deterministic하게 생성해주는 방법과 Pseudo Random Pattern Generator(PRPG)를 이용하여 생성하는 경우로 구분할 수 있다. 본 연구에서는 PRPG를 패턴 생성기로 사용하여 여러 가지 메모리의 결함을 대표한다고 볼 수 있는 Static 및 Dynamic Neighborhood Pattern Sensitive Fault(NPSF) 등 다양한 종류의 고장을 점검할 수 있도록 메모리 BIST를 구성하였다. 기존의 Linear Feedback Shift Register(LFSR)보다 본 연구에서 제안하는 Linear Hybrid Cellular Automata(LHCA)를 이용한 PRPG가 높고 안정된 고장 점검도를 나타내었다.

• 한국전기전자재료학회논문지
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• 제21권3호
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• pp.272-278
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• 2008

This paper investigated the a-si:H gate driver with the stepwise gate signal. In 1-chip type mobile LCD application the stepwise gate signal for low power consumption can be used by adding simple switching circuit. The power consumption of the a-Si:H gate driver can be decreased by employing the stepwise gate signal in the conventional circuit. In conventional one, the effect of stepwise gate signal can decrease slew rate and increase the fluctuation of gate-off state voltage, In order to increase the slew rate and decrease the gate off state fluctuation, we proposed a new a-Si:H TFT gate driver circuit. The simulation data of the new circuit show that the slew rate and the gate-off state fluctuation are improved, so the circuit can work reliably.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 제39회 하계학술대회
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• pp.1957-1958
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• 2008

The Logic Built In Self Test (LBIST) technique is substantially applied in chip design in most many semiconductor company in despite of unavoidable overhead like an increase in dimension and time delay occurred as it used. Currently common LBIST software uses the MISR (Multiple Input Shift Register) However, it has many considerations like defining the X-value (Unknown Value), length and number of Scan Chain, Scan Chain and so on for analysis of result occurred in the process. So, to solve these problems, common LBIST software provides the solution method automated. Nevertheless, these problems haven't been solved automatically by Tri-state Bus in logic circuit yet. This paper studies the simulator and algorithm that judges whether Tri-state Bus lines is the circuit which have X-value or One-hot Value after presuming the control signal of the lines which output X-value in the logic circuit to solve the most serious problems.

• 한국통신학회논문지
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• 제31권2C호
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• pp.123-129
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• 2006

랜덤하게 생성된 LDPC 부호의 경우 부호화기의 복잡도가 크기 때문에 효과적인 부호화를 위하여 구조적인 설계를 필요로 한다. 본 논문에서는 효율적인 부호화기를 위해 기존에 제안된 eIRA 부호에 순환 행렬의 구조를 적용한 부호화기 구조를 제안하였다. 제안된 순환 행렬 구조는 쉬프트 레지스터를 사용하여 부호화기를 구성할 수 있으며, 순환 행렬의 사용으로 인한 성능 저하를 방지하기 위해 치환 행렬 구조에 해당하는 인터리버를 사용하였다. 제안된 부호는 LDPC 부호화기의 복잡도는 낮추면서도 기존의 부호화기의 성능과 유사한 성능을 보인다.