• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.2
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• pp.65-73
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• 2008

Security layer of the Cdma2000 1x EV-DO is currently completing standard (C.S0024-A v2.0). Accordingly, a hardware security devices, that allows to implementation requirement of the security layer described in standard document, is required to apply security function about data transferred between AT and AN of then Cdma2000 1x EV-DO environment. This paper represents design of hardware device providing EV-DO security with simulation of the security layer protocol via the FPGA platform. The SHA-1 hash algorithm for certification and service of packet data, and the AES, SEED, ARIA algorithms for data encryption are equip in this device. And paper represents implementation of hardware that applies optionally certification and encryption function after executing key-switch using key-switching algorithm.

• Journal of Mechanical Science and Technology
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• v.20 no.10
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• pp.1722-1729
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• 2006

Predicting the mechanical properties of the 3-D scaffold using finite element method (FEM) simulation is important to the practical application of tissue engineering. However, the porous structure of the scaffold complicates computer simulations, and calculating scaffold models at the pore level is time-consuming. In some cases, the demands of the procedure are too high for a computer to run the standard code. To address this problem, the representative volume element (RVE) theory was introduced, but studies on RVE modeling applied to the 3-D scaffold model have not been focused. In this paper, we propose an improved FEM-based RVE modeling strategy to better predict the mechanical properties of the scaffold prior to fabrication. To improve the precision of RVE modeling, we evaluated various RVE models of newly designed 3-D scaffolds using FEM simulation. The scaffolds were then constructed using microstereolithography technology, and their mechanical properties were measured for comparison.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.60-68
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• 2009

This work proposes a 10b 200MS/s 65nm CMOS ADC for high-definition video systems such as HDTV requiring high resolution and fast operating speed simultaneously. The proposed ADC employs a four-step pipeline architecture to minimize power consumption and chip area. The input SHA based on four capacitors reduces the output signal range from $1.4V_{p-p}$ to $1.0V_{p-p}$ considering high input signal levels at a low supply voltage of 1.2V. The proposed three-stage amplifiers in the input SHA and MDAC1 overcome the low output resistance problem as commonly observed in a 65nm CMOS process. The proposed multipath frequency-compensation technique enables the conventional RNMC based three-stage amplifiers to achieve a stable operation at a high sampling rate of 200MS/s. The conventional switched-bias power-reduction technique in the sub-ranging flash ADCs further reduces power consumption while the reference generator integrated on chip with optional off-chip reference voltages allows versatile system a locations. The prototype ADC in a 65nm CMOS technology demonstrates a measured DNL and INL within 0.19LSB and 0.61LSB, respectively. The ADC shows a maximum SNDR of 54.BdB and 52.4dB and a maximum SFDR of 72.9dB and 64.8dB at 150MS/S and 200MS/s, respectively. The proposed ADC occupies an active die area of $0.76mm^2$ and consumes 75.6mW at a 1.2V supply voltage.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.3
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• pp.46-55
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• 2016

This work proposes a 13b 100MS/s 45nm CMOS ADC with a high dynamic performance for IF-domain high-speed signal processing systems based on a four-step pipeline architecture to optimize operating specifications. The SHA employs a wideband high-speed sampling network properly to process high-frequency input signals exceeding a sampling frequency. The SHA and MDACs adopt a two-stage amplifier with a gain-boosting technique to obtain the required high DC gain and the wide signal-swing range, while the amplifier and bias circuits use the same unit-size devices repeatedly to minimize device mismatch. Furthermore, a separate analog power supply voltage for on-chip current and voltage references minimizes performance degradation caused by the undesired noise and interference from adjacent functional blocks during high-speed operation. The proposed ADC occupies an active die area of $0.70mm^2$, based on various process-insensitive layout techniques to minimize the physical process imperfection effects. The prototype ADC in a 45nm CMOS demonstrates a measured DNL and INL within 0.77LSB and 1.57LSB, with a maximum SNDR and SFDR of 64.2dB and 78.4dB at 100MS/s, respectively. The ADC is implemented with long-channel devices rather than minimum channel-length devices available in this CMOS technology to process a wide input range of $2.0V_{PP}$ for the required system and to obtain a high dynamic performance at IF-domain input signal bands. The ADC consumes 425.0mW with a single analog voltage of 2.5V and two digital voltages of 2.5V and 1.1V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.5 s.347
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• pp.54-63
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• 2006

This work proposes a 14b 100MS/s 0.18um CMOS ADC with optimized resolution, conversion speed, die area, and power dissipation to obtain the performance required in the fourth-generation mobile communication systems. The 3-stage pipeline ADC, whose optimized architecture is analyzed and verified with behavioral model simulations, employs a wide-band low-noise SHA to achieve a 14b level ENOB at the Nyquist input frequency, 3-D fully symmetric layout techniques to minimize capacitor mismatch in two MDACs, and a back-end 6b flash ADC based on open-loop offset sampling and interpolation to obtain 6b accuracy and small chip area at 100MS/s. The prototype ADC implemented in a 0.18um CMOS process shows the measured DNL and INL of maximum 1.03LSB and 5.47LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 59dB and 72dB, respectively, and a power consumption of 145mW at 100MS/s and 1.8V. The occupied active die area is $3.4mm^2$.

• Journal of Electrical Engineering and Technology
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• v.7 no.5
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• pp.730-735
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• 2012

This paper presents a method to design the waveform of a back electromotive force (back EMF) of an axial flux permanent magnet (AFPM) motor using printed circuit board (PCB) windings. When the magnetization distribution of permanent magnet (PM) is given, the magnetic field in the air gap region is calculated by the quasi three dimensional (3D) space harmonic analysis (SHA) method. Once the flux density distribution in the winding region is determined, the required shape of the back EMF can be obtained by adjusting the winding distribution. This can be done by modifying the distance between patterns of PCB to control the harmonics in the winding distribution. The proposed method is verified by finite element analysis (FEA) results and it shows the usefulness of the method in eliminating a specific harmonic component in the back EMF waveform of a motor.

• Journal of Power Electronics
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• v.10 no.3
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• pp.245-250
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• 2010

Input-series-output-parallel (ISOP) converters consisting of multiple modular DC/DC converters can enable low voltage rating switches to be used under high voltage input applications. This paper presents a digital control strategy, which can achieve equal sharing of input voltage for a modular ISOP system consisting of two-transistor forward DC/DC converters by forcing the input voltages of neighboring modules to be equal. The proposed scheme is analyzed using small signals analysis based on the state space average method. The performance of the proposed control strategy is verified with an experimental prototype of an ISOP converter made up of three two-switch forward converters.

• Korean Journal of Microbiology
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• v.27 no.3
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• pp.259-264
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• 1989

The adherence of $^{3}H$-labeled oral streptococcal cells to protein-coated hydroxyapatite (HA) beads was studied by a standard adherence assay. The adherence equilibrium for S. mutans 10449 occured in about 2 hrs. The cell numbers adhering to SHA was 50% less than those on bare HA. Sailva from different subjects had varying effect on bacterial adherence. The use of saliva adsorbed with homologouis bacteria decreased S. mutans adherence by 38% ; this indicates the presence of salivary agglutinin in acquired pellicle formed on HA. Animal sera and BSA decreased S. sanguis adherence. BSA concentration as high as 10mg/ml caused up to 87% adherence inhibition. The desorption experiment of adhered bacteria confirmed the previous reports that the adhesive sites on HA beads for S. mutans were different from those for S. sanguis and that S. mutans could enhance the adherence of S. sanguis but not vice versa.

• Membrane and Water Treatment
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• v.3 no.4
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• pp.211-219
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• 2012

To enhance the efficiency of water treatment and reduce the extent of membrane fouling, the membrane separation process is frequently preceded by other physico-chemical processes. One of them might be ion exchange. The aim of this work was to compare the efficiency of natural organic matter removal achieved with various anion-exchange resins, and to verify their potential use in water treatment prior to the ultrafiltration process involving a ceramic membrane. The use of ion exchange prior to ceramic membrane ultrafiltration enhanced final water quality. The most effective was MIEX, which removed significant amounts of the VHA, SHA and CHA fractions. Separation of uncharged fractions was poor with all the resins examined. Water pretreatment involving an ion-exchange resin failed to reduce membrane fouling, which was higher than that observed in unpretreated water. This finding is to be attributed to the uncharged NOM fractions and small resin particles that persisted in the water.