• Title/Summary/Keyword: Serial Key

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Implementation of Modular Multiplication and Communication Adaptor for Public Key Crytosystem (공개키 암호체계를 위한 Modular 곱셈개선과 통신회로 구현에 관한 연구)

  • 한선경;이선복;유영갑
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.16 no.7
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    • pp.651-662
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    • 1991
  • An improved modular multiplication algorithm for RSA type public key cryptosystem and its application to a serial communication cricuit are presented. Correction on a published fast modular multiplication algorithm is proposed and verified thru simulation. Cryptosystem for RS 232C communication protocol isdesigned and prototyped for low speed data exchange between computers. The system adops the correct algoroithm and operates successfully using a small size key.

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Design and Implementation of Serial Key Certification System Using Smartcard (스마트카드를 이용한 시리얼 키 인증 시스템 구현 및 설계)

  • Kim, Yu-Doo;Moon, Il-Young
    • Journal of Advanced Navigation Technology
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    • v.11 no.4
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    • pp.473-478
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    • 2007
  • Current certification system use serial key for protect copyright of software and digital contents. But It is not efficient system, because It is not protect copyright through create virtual key or use public key. So we research on various cryptology for prevent illegal copy of serial key, but It is not enough protection of copyright that use software technology only. In this paper, we propose certification system using smart card for protect copyright of software and digital contents.

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3X Serial GF(2m) Multiplier on Polynomial Basis Finite Field (Polynomial basis 방식의 3배속 직렬 유한체 곱셈기)

  • 문상국
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2004.05b
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    • pp.255-258
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    • 2004
  • Efficient finite field operation in the elliptic curve (EC) public key cryptography algorithm, which attracts much of latest issues in the applications in information security, is very important. Traditional serial finite multipliers root from Mastrovito's serial multiplication architecture. In this paper, we adopt the polynomial basis and propose a new finite field multiplier, inducing numerical expressions which can be applied to exhibit 3 times as much performance as the Mastrovito's. We described the proposed multiplier with HDL to verify and evaluate as a proper hardware IP. HDL-implemented serial GF (Galois field) multiplier showed 3 times as fast speed as the traditional serial multiplier's adding only Partial-sum block in the hardware.

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Design and Analysis of a Digit-Serial $AB^{2}$ Systolic Arrays in $GF(2^{m})$ ($GF(2^{m})$ 상에서 새로운 디지트 시리얼 $AB^{2}$ 시스톨릭 어레이 설계 및 분석)

  • Kim Nam-Yeun;Yoo Kee-Young
    • Journal of KIISE:Computer Systems and Theory
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    • v.32 no.4
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    • pp.160-167
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    • 2005
  • Among finite filed arithmetic operations, division/inverse is known as a basic operation for public-key cryptosystems over $GF(2^{m})$ and it is computed by performing the repetitive $AB^{2}$ multiplication. This paper presents a digit-serial-in-serial-out systolic architecture for performing the $AB^2$ operation in GF$(2^{m})$. To obtain L×L digit-serial-in-serial-out architecture, new $AB^{2}$ algorithm is proposed and partitioning, index transformation and merging the cell of the architecture, which is derived from the algorithm, are proposed. Based on the area-time product, when the digit-size of digit-serial architecture, L, is selected to be less than about m, the proposed digit-serial architecture is efficient than bit-parallel architecture, and L is selected to be less than about $(1/5)log_{2}(m+1)$, the proposed is efficient than bit-serial. In addition, the area-time product complexity of pipelined digit-serial $AB^{2}$ systolic architecture is approximately $10.9\%$ lower than that of nonpipelined one, when it is assumed that m=160 and L=8. Additionally, since the proposed architecture can be utilized for the basic architecture of crypto-processor and it is well suited to VLSI implementation because of its simplicity, regularity and pipelinability.

A Study on the Forms of Serial Expression in Contemporary Fashion Design (현대 패션디자인의 연속 표현[serial expression]형식에 관한 연구)

  • Kwon, Ja-Young;Geum, Key-Sook
    • Journal of the Korean Society of Costume
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    • v.57 no.8
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    • pp.114-124
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    • 2007
  • Contemporary fashion design has been represented as intermedia transcended value and spatiotemporal notion and also had a tendency to concentrate on serial process that materials are transfigured through time rather than existence. These forms related to interaction with time, space and performance as well as compositive genres, hybrid culture, compound gender define as 'serial expression' in this study. The serial expression ran be characterized that system, process, series, enumeration of sequences, depiction of performance, repetition of action in fashion collections and exhibitions of designers. The concept and circumstances made by author as a creator of fashion broaden perceptions of audiences and arouse spectators to participate in the situation as needing immediate attention. The forms of fashion and Conceptual Art in serial expression are analogous and even identical situations represent in fashion collection. Therefore analysis serial forms of art derives formative features: Narrative process, Imitation and Appropriation, Virtual reality and High technology, Hybridism and Convergence. This study suggest a framework to analyze conceptual fashion that give salience to megatrend in contemporary fashion culture on artistic point of view.

Development of Self-Checking characteristics Serial Data Distribution Module (자기검사특성을 갖는 시리얼데이터 분배모듈의 개발)

  • Shin, Duck-Ho;Lee, Jong-Woo;Kim, Jong-Ki;Lee, Key-Soe
    • Proceedings of the KIEE Conference
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    • 2002.07d
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    • pp.2240-2242
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    • 2002
  • This paper show serial communication method in order to design how to interface between fault tolerant systems with redundancy. Problem has been in the method that fault tolerant system had switched of serial data with common switching device. This problem degrade reliability in itself and total system which is interfaced with that serial communication system. So Arbitration module of serial communication which is suggested in this paper can improve the reliability using voter algorithm which fault is detected passively.

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Effect of serial Characteristics and Library Environment on Serial Collection Decision in an Academic Health Science Library (의학분야 학술잡지 선택에 영향을 미치는 요인 연구)

  • Kim, Gi-Yeong
    • Journal of the Korean Society for information Management
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    • v.23 no.2
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    • pp.245-263
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    • 2006
  • Since the beginning of discussions on serial collection management, as budgets have waxed and waned over the ensuing decades, a number of key variables affecting selection/deselection have emerged but without the framework of a coherent and accepted theoretical model. This study is an effort to identify variables which affect the serial collection decision with special attention to selection/deselection in the context of an academic health science library. Based on results from correlation analyses and logistic regression analyses, the serial collection decision can be explained and predicted using various combinations of a reduced set of objective variables. Applications of the results to libraries are discussed, and further research is proposed.

A Comparative Study of Metadata Standards for Serials (학술지 메타데이터의 표준화 체계에 관한 비교 연구)

  • Han Sung-Kook;Lee Hyun-Sil
    • Journal of Korean Library and Information Science Society
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    • v.36 no.1
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    • pp.415-440
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    • 2005
  • This paper analyses meta-data systems for serials in order to provide the fundamental infrastructure for serials-sharing systems based on semantic interoperability. According to the primitive features of serials information, meta-data for serials are classified into 3 main subsystems: serial identification Information, serial bibliographic information and serial holding information. The serial identification information that play the important role of the primary key in library management systems should be refined to accommodate serials with digital formats. Although MARC formats have been commonly used for the description of serial bibliographic information, a new meta-data format for serial bibliographic information that harmonize with the abundance of meta-data elements in MARC and the simplicity of DCMI. For serial holding information, the newly proposed standards such as ANSI/NSIO Z39.50 are adequate to grasp the varieties of serial holding patterns. It should be able to differentiate the level of description by means of the types of serial information services. As the current computing technology generally uses XML for the representation and Process of information, the meta-data system for serials should be based on XML.

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3X Serial GF($2^m$) Multiplier Architecture on Polynomial Basis Finite Field (Polynomial basis 방식의 3배속 직렬 유한체 곱셈기)

  • Moon, Sang-Ook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.10 no.2
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    • pp.328-332
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    • 2006
  • Efficient finite field operation in the elliptic curve (EC) public key cryptography algorithm, which attracts much of latest issues in the applications in information security, is very important. Traditional serial finite multipliers root from Mastrovito's serial multiplication architecture. In this paper, we adopt the polynomial basis and propose a new finite field multiplier, inducing numerical expressions which can be applied to exhibit 3 times as much performance as the Mastrovito's. We described the proposed multiplier with HDL to verify and evaluate as a proper hardware IP. HDL-implemented serial GF (Galois field) multiplier showed 3 times as fast speed as the traditional serial multiplier's adding only partial-sum block in the hardware. So far, there have been grossly 3 types of studies on GF($2^m$) multiplier architecture, such as serial multiplication, array multiplication, and hybrid multiplication. In this paper, we propose a novel approach on developing serial multiplier architecture based on Mastrovito's, by modifying the numerical formula of the polynomial-basis serial multiplication. The proposed multiplier architecture was described and implemented in HDL so that the novel architecture was simulated and verified in the level of hardware as well as software.

Improved Reliability-Based Iterative Decoding of LDPC Codes Based on Dynamic Threshold

  • Ma, Zhuo;Du, Shuanyi
    • ETRI Journal
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    • v.37 no.4
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    • pp.736-742
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    • 2015
  • A serial concatenated decoding algorithm with dynamic threshold is proposed for low-density parity-check codes with short and medium code lengths. The proposed approach uses a dynamic threshold to select a decoding result from belief propagation decoding and order statistic decoding, which improves the performance of the decoder at a negligible cost. Simulation results show that, under a high SNR region, the proposed concatenated decoder performs better than a serial concatenated decoder without threshold with an Eb/N0 gain of above 0.1 dB.