• Journal of Korean Society of Industrial and Systems Engineering
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• v.39 no.1
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• pp.153-161
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• 2016

Semiconductor manufacturing has suffered from the complex process behavior of the technology oriented control in the production line. While the technological processes are in charge of the quality and the yield of the product, the operational management is also critical for the productivity of the manufacturing line. The fabrication line in the semiconductor manufacturing is considered as the most complex part because of various kinds of the equipment, re-entrant process routing and various product devices. The efficiency and the productivity of the fabrication line may give a significant impact on the subsequent processes such as the probe line, the assembly line and final test line. In the management of the re-entrant process such as semiconductor fabrication, it is important to keep balanced fabrication line. The Performance measures in the fabrication line are throughput, cycle time, inventory, shortage, etc. In the fabrication, throughput and cycle time are the conflicting performance measures. It is very difficult to achieve two conflicting goal simultaneously in the manufacturing line. The capacity of equipment is important factor in the production planning and scheduling. The production planning consideration of capacity can make the scheduling more realistic. In this paper, an input and scheduling rule are to achieve the balanced operation in semiconductor fabrication line through equipment capacity and workload are proposed and evaluated. New backward projection and scheduling rule consideration of facility capacity are suggested. Scheduling wafers on the appropriate facilities are controlled by available capacity, which are determined by the workload in terms of the meet the production target.

• Journal of the Semiconductor & Display Technology
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• v.21 no.2
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• pp.74-84
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• 2022

As the semiconductor industry develops, the difficulty of newly required process technology becomes difficult, and the importance of production yield and product reliability increases. As an effort to minimize yield loss in the manufacturing process, interests in the process defect process for facility diagnosis and defect identification are continuously increasing. This research observed the plasma condition changes in the multi oxide/nitride layer deposition (MOLD) process, which is one of the 3D-NAND manufacturing processes through optical emission spectroscopy (OES) and monitored the result of whether the change in plasma characteristics generated in repeated deposition of oxide film and nitride film could directly affect the film. Based on these results, it was confirmed that if a change over a certain period occurs, a change in the plasma characteristics was detected. The change may affect the quality of oxide film, such as the film thickness as well as the interfacial surface roughness when the oxide and nitride thin film deposited by plasma enhenced chemical vapor deposition (PECVD) method.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.4
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• pp.1812-1816
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• 2011

This research developed chemical flow control system(CFCS) essential for spinner equipment in nano semiconductor manufacturing process under the 100nm to prevent complex process defect due to missing spread after chemical injection. The devices developed in this research, which can be swiftly replaced in case abnormal state element changes or wafer manufacturing defect occurs, are anticipated to improve module yield as well as real-time monitoring on the state element. In addition, as a result of mounting H/W and S/W system to control detailed operation sequence in production line and executing performance check and verification, we can be exactly detected in five abnomal process type.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.44-44
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• 2009

Fault detection is necessary for yield enhancement and cost reduction in semiconductor manufacturing. Sensory data acquired from the semiconductor processing tool is too large to analyze for the purpose of fault detection and classification(FDC). We studied the techniques of fault detection using statistical method. Multiple regression analysis smoothly detected faults and can be easy made a model. For real-time and fast computing time, the huge data was analyzed by each step. We also considered interaction and critical factors in tool parameters and process.

• Journal of the Semiconductor & Display Technology
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• v.19 no.3
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• pp.12-18
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• 2020

In semiconductor manufacturing, defect detection is critical to maintain high yield. Currently, computer vision systems used in semiconductor photo lithography still have adopt to digital image processing algorithm, which often occur inspection faults due to sensitivity to external environment. Thus, we intend to handle this problem by means of using Mask R-CNN instead of digital image processing algorithm. Additionally, Mask R-CNN can be trained with image dataset pre-processed by means of the specific designed digital image filter to extract the enhanced feature map of Convolutional Neural Network (CNN). Our approach converged advantage of digital image processing and instance segmentation with deep learning yields more efficient semiconductor photo lithography inspection system than conventional system.

• Journal of the Semiconductor & Display Technology
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• v.23 no.2
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• pp.135-142
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• 2024

Cu-Cu bonding, one of the key technologies in advanced packaging, enhances semiconductor chip performance, miniaturization, and energy efficiency by facilitating rapid data transfer and low power consumption. However, the quality of the interface bonding can significantly impact overall bond quality, necessitating strategies to quickly detect and classify in-process defects. This study presents a methodology for detecting defects in wafer junction areas from Scanning Acoustic Microscopy images using a ResNet-50 based deep learning model. Additionally, the use of the defect map is proposed to rapidly inspect and categorize defects occurring during the Cu-Cu bonding process, thereby improving yield and productivity in semiconductor manufacturing.

• IE interfaces
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• v.22 no.2
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• pp.126-134
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• 2009

As product quality and yield are essential factors in semiconductor manufacturing, monitoring the main manufacturing steps is a critical task. For the purpose, FDC(Fault detection and classification) is used for diagnosing fault states in the processes by monitoring data stream collected by equipment sensors. This paper proposes an FDC model based on decision tree which provides if-then classification rules for causal analysis of the processing results. Unlike previous decision tree approaches, we reflect the structural aspect of the data stream to FDC. For this, we segment the data stream into multiple subregions, define structural features for each subregion, and select the features which have high relevance to results of the process and low redundancy to other features. As the result, we can construct simple, but highly accurate FDC model. Experiments using the data stream collected from etching process show that the proposed method is able to classify normal/abnormal states with high accuracy.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.9
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• pp.4467-4471
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• 2013

In this research, developed full-scan photoresist coating system(FPCS) can improve the efficiency of the photoresist coating system essential for spinner equipment in nano semiconductor manufacturing process. The devices developed in this research, which can be swiftly replaced in case abnormal state element changes or wafer manufacturing defect occurs, are anticipated to improve module yield as well as real-time monitoring on the state element in order to prevent the complex process defect due to the photoresist miss coating.

• Journal of the Semiconductor & Display Technology
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• v.5 no.1 s.14
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• pp.5-11
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• 2006

One of the most important is to insure that a new circuit design is qualified far release before it is scheduled for manufacturing, test, assembly and delivery. Due to various causes, there happens to be a low yield in the wafer process. Wafer test is a critical process in analyzing the chip characteristics in the EDS(electric die sorting) using analytic tools -wafer map, wafer summary and datalog. In this paper, we propose new analytic map algorithms for DDI chip test data. Using the proposed analytic map algorithms, we expect to improve the yield, quality and analysis time.

• The Journal of Information Systems
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• v.26 no.2
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• pp.105-121
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• 2017

Purpose It is a major goal to improve the product yields during production operations in the manufacturing industry. Therefore, factory is trying to keep the good quality materials and proper production resources, also find the proper condition of facilities and manufacturing environment for yields improvement. Design/methodology/approach We propose the hybrid framework to analyze to dataset extracted from MES. Those data is about the alarm information generated from equipment, both measurement and equipment process value from production and cycle/pitch time measured from production data these covered products during production. We adapt a data warehousing techniques for organizing dataset, a logistic regression for finding out the significant factors, and a association analysis for drawing the rules which affect the product yields. And then we validate the framework by applying the real data generated from the discrete process in secondary cell battery manufacturing. Findings This paper deals with challenges to apply the full potential of modeling and simulation within CPPS(Cyber-Physical Production System) and Smart Factory implementation. The framework is being applied in one of the most advanced and complex industrial sectors like semiconductor, display, and automotive industry.