• Journal of Energy Engineering
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• v.22 no.1
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• pp.58-81
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• 2013

Recently, the technological progress in manufacturing power devices based on wide bandgap materials, for example, silicon carbide(SiC) or gallium nitride(GaN), has resulted in a significant improvement of the operating-voltage range and switching speed and/or specific on resistance compared with silicon power devices. This paper will give an overview of the status on The Next generation Power Devices such as SiC/GaN with a focus on commercialization and research.

• IE interfaces
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• v.11 no.3
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• pp.65-75
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• 1998

This research considers the problem of scheduling jobs on parallel machines with non-common due dates and additional resource constraints. The objective is to minimize the total absolute deviation of job completion times about the due dates. Job processing times are assumed to be the same. This problem is motivated by restrictions that occur in the handling and processing of jobs in certain phases of semiconductor manufacturing and other production systems. We examine two problems. For the first of these, the number of different types of additional: resources and resource requirements per job are arbitrary. The problem is formulated as a zero-one integer linear programming and the Lagrangian relaxation approach is used. For the second case, there exists one single type of additional resource and the resource requirements per job are zero or one. We show how to formulate the problem as an assignment problem.

• IE interfaces
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• v.10 no.1
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• pp.79-93
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• 1997

지난 30여 년간 반도체 제조 공정 중 FAB공정에서 칩 수율 모델의 개발과 적용은 반도체생산 계획 및 조업 관리를 위해 반도체 제조사들에게는 중요한 관리 대상이 되어 왔으며 제조업체들은 다양한 수율 모델들을 각 업체의 조건에 맞게 채택, 적용하여 왔다. 집적 기술의 발전은 반도체 칩의 크기에도 변화를 가져와 웨이퍼상의 결점들이 형성하는 클러스터를 설명할 수 있어야 했으며 칩 면적의 증가는 새로운 수율 모델을 개발케 하였다. 본 논문은 반도체 제조 공정에 대한 고찰과 수율 계산에 영향을 미치는 결점의 클러스터 효과 및 결점 크기를 중심으로 하는 치명 확률에 대하여 살펴보고, 포아송 모델에서 파생된 대표적인 칩 수율 모델들에 대한 설명과 칩 면적의 변화에 따른 각 모델별 수율 계산 비교 및 반도체 수율의 이용에 대하여 기술한다.

• Proceedings of the KIPE Conference
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• 2004.07b
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• pp.878-882
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• 2004

Position controls are very important in semiconductor manufacturing devices, machine tools precision measuring instruments, etc. In this paper, a novel encoder of digital and analog hybrid type is proposed. It is shown that from this experiment a high-resolution angle measurement device can be designed by a low cost incremental encoder.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.828-831
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• 2001

A simple and versatile method of manufacturing semiconductor devices with pn-junctions used the silicon direct bonding technology with simultaneous impurity diffusion is suggested . Formation of p- or n- type layers was tried during the bonding procedure by attaching two wafers in the aqueous solutions of Al(NO$_3$)$_3$, Ga(NO$_3$)$_3$, HBO$_3$, or H$_3$PO$_4$. An essential improvement of bonding interface structural quality was detected and a model for the explanation is suggested. Diode, Dynistor, and BGGTO structures were fabricated and examined. Their switching characteristics are presented.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.10
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• pp.779-784
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• 2001

In this work, we studied the characteristics of nitride films for the optimization of PMD(pro-metal dielectric) linear process, which can be applied to the recent semiconductor manufacturing process. We split the deposit condition of nitride films into four parts such as PO(protect overcoat) nitride, baseline, low hydrogen and high stress and low hydrogen, respectively. We tried to find out correlation between BPSG deposition and densification. In order to analyze the changes of Si-H and Si-NH-Si bonding density, we used FTIR area method. We also investigated the crack generation on wafer edge after BPSG densification, and the changes of nitride film stress as a function of RF power variation to judge whether the deposited films.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.22-23
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• 2006

A process for removal of photoresist(PR) m semiconductor manufacturing using water vapor with ozone is presented. For the realization of the ozone/vapor mixture process, high concentration ozone generator and process facilities have developed. As a result of the silicon wafer PR strip test, we confirmed the high efficiency PR strip rates of 400nm/mm or more at the ozone concentration of 16wt%/$O_2$. The ozone/vapor mixture process is more effective than the ozonized water Immersion process.

• Journal of Integrative Natural Science
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• v.2 no.1
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• pp.13-17
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• 2009

A newly developed OTFT manufacturing process using the combination of self-assembly techniques and vapor phase polymerization method revealed that a thick $SiO_2$ dielectric layer (100~200 nm) is not well compatible with conducting polymer electrode, thereby resulting in still recognizable contact resistance, unstable $V_{th}$ and leaking off current. A couple of very recent studies showed that this issue may be solved by replacing such inorganic dielectric with a self-assembled monolayer or multilayer (organic) dielectric. Therefore, this short review introduces recent trends in the development of high performance thin film transistor consisting of both organic semiconductor and SAM dielectric.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.35 no.1
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• pp.79-86
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• 2012

This study focuses on the problem of scheduling wafer lots of several recipe(operation condition) types in the photolithography workstation in a semiconductor wafer fabrication facility, and sequence-dependent recipe set up times may be required at the photolithography machines. In addition, a lot is able to be operated at a machine when the reticle(mask) corresponding to the recipe type is set up in the photolithography machine. We suggest various heuristic algorithms, in which developed recipe selection rules and lot selection rules are used to generate reasonable schedules to minimizing the total weighted flowtime. Results of computational tests on randomly generated test problems show that the suggested algorithms outperform a scheduling method used in a real manufacturing system in terms of the total weighted flowtime of the wafer lots with ready times.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.32 no.3
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• pp.99-109
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• 2009

Negative binomial yield model for semiconductor manufacturing consists of two parameters which are the average number of defects per die and the clustering parameter. Estimating the clustering parameter is quite complex because the parameter has not clear closed form. In this paper, a Bayesian approach using Markov Chain Monte Carlo is proposed to estimate the clustering parameter. To find an appropriate estimation method for the clustering parameter, two typical estimators, the method of moments estimator and the maximum likelihood estimator, and the proposed Bayesian estimator are compared with respect to the mean absolute deviation between the real yield and the estimated yield. Experimental results show that both the proposed Bayesian estimator and the maximum likelihood estimator have excellent performance and the choice of method depends on the purpose of use.