• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.101-102
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• 2005

SiC lateral power semiconductor device has high breakdown voltage and low on-state voltage drop due to the material characteristics. And, because the high breakdown voltage can be obtained, RESURF technique is mostly used in silicon power semiconductor devices. In this paper, we presents the electrical characteristics of the 4H-SiC RESURF LDMOSFET as a function of the epi-layer length, concentration and thickness. 240~780V of breakdown voltage can be obtained as a function of epi-layer length and thickness with same epi-layer concentration.

• 반도체디스플레이기술학회지
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• 제17권1호
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• pp.35-39
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• 2018

This paper deals with the relaxation of singular stresses developed in an epoxy adhesive at high temperature. The interface stresses are analyzed using BEM. The adhesive employed in this study is an epoxy which can be cured at room temperature. The adhesive is assumed to be linearly viscoelastic. First, the distribution of the interface stresses developed in the adhesive layer under the uniform tensile stress has been calculated. The singular stress has been observed near the interface corner. Such singular stresses near the interface corner may cause epoxy layer separated from adherent. Second, the interfacial thermal stress has been investigated. The uniform temperature rise can relieve the stress level developed in the adhesive layer under the external loading, which can be viewed as an advantage of thermal loading. It is also obvious that temperature rise reduces the bonding strength of the adhesive layer. Experimental evaluation is required to assess a trade-off between the advantageous and deleterious effects of temperature.

• 한국재료학회지
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• 제29권7호
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• pp.408-411
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• 2019

ZTO/n-Si thin film is produced to investigate tunneling phenomena by interface characteristics by the depletion layer. For diversity of the depletion layer, the thin film of ZTO is heat treated after deposition, and the gpolarization is found to change depending on the heat treatment temperature and capacitance. The higher the heat treatment temperature is, the higher the capacitance is, because more charges are formed, the highest at $150^{\circ}C$. The capacitance decreases at $200^{\circ}C$ ZTO heat treated at $150^{\circ}C$ shows tunneling phenomena, with low non-resistance and reduced charge concentration. When the carrier concentration is low and the resistance is low, the depletion layer has an increased potential barrier, which results in a tunneling phenomenon, which results in an increase in current. However, the ZTO thin film with high charge or high resistance shows a Schottky junction feature. The reason for the great capacitance increase is the increased current due to tunneling in the depletion layer.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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• pp.204.2-204.2
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• 2015

산화물 반도체는 비정질임에도 불구하고 높은 이동도를 나타내며, 적은 누설 전류, 낮은 소비전력, 저온 공정 가능, 가시광선 영역에서 투명한 성질을 가지고 있다. 이와 같은 다양한 장점들로 인해 산화물 반도체를 이용한 트랜지스터는 차세대 플랫 패널 디스플레이 적용에 있어서 핵심 기술로 각광받고 있다. 한편, 소자의 크기가 점점 더 작아짐에 따라 고집적화에 따른 scaling down은 항상 언급되는 이슈이다. 이와 관련하여 소자의 높은 on current는 트랜지스터를 더 작게 구현할 수 있다는 가능성을 보여준다. 따라서 현재 소자의 on current를 높이기 위해서 소자의 구조를 변형하는 연구가 활발히 진행되고 있다. 본 연구에서는 소자의 on current를 높이기 위한 방법으로 ITO buried layer를 이용한 산화물 반도체 pseudo 트랜지스터를 제작하였다. 먼저 채널을 형성하기 전에 ITO buried layer를 형성시켜준 후, 채널 영역으로서 InGaZnO (2:1:1)를 용액 공정을 이용하여 형성시켰다. 이어서 소자의 전기적 특성 향상을 위해 마이크로웨이브 열처리를 1800 W에서 2분간 실시하였다. 또한 대조군으로 ITO buried layer를 갖지 않는 소자를 같은 방법으로 제작하여 평가하였다. 그 결과 ITO buried later를 갖는 소자에서 대조군과 비교하여 높은 on current를 나타냄을 확인하였다. 이와 같은 결과는 낮은 저항의 ITO buried layer가 current path를 제공함과 동시에 더 두꺼운 채널 층을 형성시켜 높은 on current에 기여하기 때문이다. 결과적으로 ITO buried layer를 갖는 소자 구조를 이용함으로써 고성능 트랜지스터를 제작하여 소자를 집적화 함에 있어서 유망한 소자가 될 것으로 예상된다.

• 반도체디스플레이기술학회지
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• 제12권3호
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• pp.23-27
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• 2013

This paper is for enhancing the breakdown voltage of MHEMTs with an InP-etchstop layer. Gate-recess structures has been simulated and analyzed for the breakdown of the devices with the InP-etchstop layer. The fully removed recess structure in the drain side of MHEMT shows that the breakdown voltage enhances from 2V to almost 4V and that the saturation current at gate voltage of 0V is reduced from 90mA to 60mA at drain voltage of 2V. This is because the electron-captured negatively fixed charges at the drain-side interface between the InAlAs barrier layer and the $Si_3N_4$ passivation layer deplete the InGaAs channel layer more and thus decreases the electron current passing the channel layer. In the paper, the fully-recessed asymmetric gate-recess structure at the drain side shows the on-breakdown voltage enhancement from 2V to 4V in the MHEMTs.

• 반도체디스플레이기술학회지
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• 제20권3호
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• pp.22-26
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• 2021

Thin-film encapsulation (TFE) technology is most effective in preventing water vapor and oxygen permeation in the organic light emitting diodes (OLED). Of those, a laminated structure of Al₂O₃ and MgO were applied to provide efficient barrier performance for increasing the stability of devices in air. Atomic layer deposition (ALD) method is known as the most promising technology for making the laminated Al₂O₃/MgO and is used to realize a thin film encapsulation technology in organic light-emitting diodes. Atomic layer deposited inorganic films have superior barrier performance and have advantages of excellent uniformity over large scales at relatively low deposition temperatures. In this study, the control system of the MgCP₂ precursor for the atomic layer deposition of MgO was established in order to deposit the MgO layer stably by the injection time of second level and the stable heating temperature. The deposition rate was obtained stably to be from 4 to 10 Å/cycle using the injection pulse times ranging from 3 to 12 sec and a substrate temperature ranging from 80 to 150 ℃.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 C
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• pp.2004-2006
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• 1996

A thermally driven polysilicon micro actuator has been fabricated using surface micromachining techniques. It consists of P-doped polysilicon as a structural layer and TEOS (tetracthylorthosilicate) as a sacrificial layer. The polysilicon was annealed for the relaxation of residual stress which is the main cause to its deformation such as bending and buckling. And the newly developed HF VPE (vapor phase etching) process was also used as an effective release method for the elimination of sacrificial TEOS layer. The thickneas of polysilicon is $2{\mu}m$ and the lengths of active and passive polysilicon cantilevers are $500{\mu}m$ and $260{\mu}m$, respectively. The actuation is incurred by die thermal expansion due to the current flow in the active polysilicon cantilever, which motion is amplified by lever mechanism. The moving distance of polysilicon micro actuator was experimentally conformed as large as $21{\mu}m$ at the input voltage level of 10V and 50Hz square wave. The actuating characteristics are investigated by simulating the phenomena of heat transfer and thermal expansion in the polysilicon layer. The displacement of actuator is analyzed to be proportional to the square of input voltage. These micro actuator technology can be utilized for the fabrication of MEMS (microelectromechanical system) such as micro relay, which requires large displacement or contact force but relatively slow response.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2009년도 춘계학술발표대회
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• pp.16.1-16.1
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• 2009

We have fabricated solution processed oxide semiconductor active layer for thin film transistors (TFTs). The oxide semiconductor layers were prepared by ink-jet printing the sol-gel precursor solution based on doped-ZnO. Inorganic ZnO-based thin films have drawn significant attention as an active channel layer for TFTs applications alternative to conventional Si-based materials and organic semiconducting materials, due to their wide energy band gap, optical transparency, high mobility, and better stability. However, in spite of such excellent device performances, the fabrication methods of ZnO related oxide active layer involve high cost vacuum processes such as sputtering and pulsed laser deposition. Herein we introduced the ink-jet printing technology to prepare the active layers of oxide semiconductor. Stable sol-gel precursor solutions were obtained by controlling the composition of precursor as well as solvents and stabilizers, and their influences on electrical performance of the transistors were demonstrated by measuring electrical parameters such as off-current, on-current, mobility, and threshold voltage. Microstructure and thermal behavior of the doped ZnO films were investigated by SEM, XRD, and TG/DTA. Furthermore, we studied the influence of the ink-jet printing conditions such as substrate temperature and surface treatment on the microstructure of the ink-jet printed active layers and electrical performance. The mobility value of the device with optimized condition was about 0.1-1.0 $cm^2/Vs$ and the on/off current ratio was about $10^6$. Our investigations demonstrate the feasibility of the ink-jet printed oxide TFTs toward successful application to cost-effective and mass-producible displays.

• 반도체디스플레이기술학회지
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• 제17권3호
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• pp.41-45
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• 2018

Two-dimensional (2D) materials have been studied extensively due to their excellent physical, chemical, and electrical properties. Among them, we report the material and device characteristics of tin disulfide ($SnS_2$). To apply $SnS_2$ as a channel layer in a transistor, $SnS_2$ channels were formed by a stripping method and a transfer method. The limitation of this method is that it is difficult to produce uniform device characteristics over a large area. Therefore, we directly deposited $SnS_2$ by atomic layer deposition (ALD) and then performed lithography. This method was able to produce devices with repeatable characteristics over a large area. However, the $SnS_2$ film was damaged by the acetone used as a photoresist (PR) developer during the lithography process, with the electrical properties of mobility of $2.6{\times}10^{-4}cm^2/Vs$, S.S. of 58.1 V/decade, and on/off current ratio of $1.8{\times}10^2$. These results are not suitable for advanced electronic devices. In this study, we analyzed the effect of acetone on $SnS_2$ and studied the device process to prevent such damage. Using polyvinyl alcohol (PVA) as a passivation layer during the lithography process, the electrical characteristics of the $SnS_2$ transistor had $2.11{\times}10^{-3}cm^2/Vs$ of mobility, 11.3 V/decade of S.S, and $2.5{\times}10^3$ of the on/off current ratio, which were 10x improvements to the $SnS_2$ transistor fabricated by the conventional method.

• 한국결정성장학회지
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• 제13권1호
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• pp.19-23
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• 2003

Polished surface of $CsB_{3}O_{5}$ (CBO) has been observed by reflection high energy electron diffraction (RHEED) and X-ray photoelectron spectroscopy (XPS). For comparison, electronic properties of CBO powder have been studied by XPS. It has been found that the crystal surface is covered by thick amorphous layer with chemical composition closely related to that of CBO. Great enrichment of top surface by cesium, ~30 % in reference to the bulk of the modified layer, has been displayed by depth profiling.