• Journal of the Korea Society for Simulation
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• v.19 no.1
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• pp.1-11
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• 2010

K company produces semiconductor package products under the make-to-order policy to supply for domestic and foreign semiconductor manufacturing companies. Its production process is a machine-paced assembly line type, which consists of die sawing, assembly, and test. This paper suggests three plans to increase process throughput based on the process analysis of K company and evaluates them via a simulation model using a real data collected. The three plans are line balancing by adding machines to the bottleneck process, product group scheduling, and reallocation of the operators in non-bottleneck processes. The evaluation result shows the highest daily throughput increase of 17.3% with an effect of 2.8% reduction of due date violation when the three plans are applied together. Payback period for the mixed application of the three plans is obtained as 1.37 years.

• International Journal of Precision Engineering and Manufacturing
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• v.2 no.2
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• pp.38-47
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• 2001

This paper decribes the development of computer-aided design of a very precise progressice die for lead frame of semiconductor chip. The approach to the system is based on knowledgr-based rules. Knowledge of fie이 experts. This system has been written in AutoLISP using AutoCAD ona personal computer and the I-DEAS drafting programming Language on the I-DEAS mater series drafting with on HP9000/715(64) workstation. Data exchange between AutoCAD and I-DEAS master series drafting is accomplished using DXF(drawing exchange format) and IGES(initial graphics exchange specification) files. This system is composed of six main modules, which are input and shape treatment, production feasibility check, strip layout, data conversion, die layout, and post processing modules. Based on Knowledge-based rules, the system considers several factors, such as V-notches, dimple, pad chamfer, spank, cavity punch, camber, coined area, cross bow, material and thickness of product, complexities of blank geometry and punch profiles, specifications of available presses, and the availability of standard parts. As forming processes and the die design system using 2D geometry recognition are integrated with the technology of process planning, die design, and CAE analysis, the standardization of die part for lead frames requiting a high precision process is possible. The die layout drawing generated by the die layout module s displayed in graphic form. The developed system makes it possible to design and manufacture lead frame of a semiconductor more efficiently.

• Transactions on Electrical and Electronic Materials
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• v.5 no.1
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• pp.19-23
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• 2004

A novel method of high speed, accurate circuit simulation in 3-dimensional (3-D) parallel-plate capacitors is investigated. The basic concept of the circuit simulation methods is partial element equivalent circuit model. The three test structures of 3-D parallel-plate capacitors are fabricated by using multi-layer low-temperature co-fired ceramic (LTCC) process and their S-parameters are measured between 50 MHz and 5 GHz. S-parameters are converted to Y-parameters, for comparing measured data with simulated data. The circuit model parameters of the each building block are optimized and extracted using HSPICE circuit simulator. This method is convenient and accurate so that circuit design applications can be easily manipulated.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.64-64
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• 2009

As the advanced packaging technology developing, Copper electro-plating processing has be wildly utilized in the semiconductor interconnect technique. Chemical solution monitoring methods, including PH and gravity measurement exist in industry, but economical and practical real-time monitoring has not been achieved yet. Red-green-blue (RGB) color sensor can successfully monitor the condition of $CuSO_4$ solution during electric copper plating process. Comparing the intensity variations of the RGB data and optical spectroscopy data, strong correlation between two in-situ sensors have shown.

• Journal of the Semiconductor & Display Technology
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• v.5 no.1 s.14
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• pp.5-11
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• 2006

One of the most important is to insure that a new circuit design is qualified far release before it is scheduled for manufacturing, test, assembly and delivery. Due to various causes, there happens to be a low yield in the wafer process. Wafer test is a critical process in analyzing the chip characteristics in the EDS(electric die sorting) using analytic tools -wafer map, wafer summary and datalog. In this paper, we propose new analytic map algorithms for DDI chip test data. Using the proposed analytic map algorithms, we expect to improve the yield, quality and analysis time.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.241-241
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• 2012

Semiconductor industry has been taking the advantage of improvements in process technology in order to maintain reduced device geometries and stringent performance specifications. This results in semiconductor manufacturing processes became hundreds in sequence, it is continuously expected to be increased. This may in turn reduce the yield. With a large amount of investment at stake, this motivates tighter process control and fault diagnosis. The continuous improvement in semiconductor industry demands advancements in process control and monitoring to the same degree. Any fault in the process must be detected and classified with a high degree of precision, and it is desired to be diagnosed if possible. The detected abnormality in the system is then classified to locate the source of the variation. The performance of a fault detection system is directly reflected in the yield. Therefore a highly capable fault detection system is always desirable. In this research, time series modeling of the data from an etch equipment has been investigated for the ultimate purpose of fault diagnosis. The tool data consisted of number of different parameters each being recorded at fixed time points. As the data had been collected for a number of runs, it was not synchronized due to variable delays and offsets in data acquisition system and networks. The data was then synchronized using a variant of Dynamic Time Warping (DTW) algorithm. The AutoRegressive Integrated Moving Average (ARIMA) model was then applied on the synchronized data. The ARIMA model combines both the Autoregressive model and the Moving Average model to relate the present value of the time series to its past values. As the new values of parameters are received from the equipment, the model uses them and the previous ones to provide predictions of one step ahead for each parameter. The statistical comparison of these predictions with the actual values, gives us the each parameter's probability of fault, at each time point and (once a run gets finished) for each run. This work will be extended by applying a suitable probability generating function and combining the probabilities of different parameters using Dempster-Shafer Theory (DST). DST provides a way to combine evidence that is available from different sources and gives a joint degree of belief in a hypothesis. This will give us a combined belief of fault in the process with a high precision.

• Industrial Engineering and Management Systems
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• v.14 no.4
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• pp.392-400
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• 2015

Monitoring of plasma etch processes for fault detection is one of the hallmark procedures in semiconductor manufacturing. Optical emission spectroscopy (OES) has been considered as a gold standard for modeling plasma etching processes for on-line diagnosis and monitoring. However, statistical quantitative methods for processing the OES data are still lacking. There is an urgent need for a statistical quantitative method to deal with high-dimensional OES data for improving the quality of etched wafers. Therefore, we propose a robust relevance vector machine (RRVM) for regression with statistical quantitative features for modeling etch rate and uniformity in plasma etch processes by using OES data. For effectively dealing with the OES data complexity, we identify seven statistical features for extraction from raw OES data by reducing the data dimensionality. The experimental results demonstrate that the proposed approach is more suitable for high-accuracy monitoring of plasma etch responses obtained from OES.

• Safety and Health at Work
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• v.11 no.4
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• pp.500-508
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• 2020

Background: Research on the status of many chemicals used in the semiconductor industry is needed. The purpose of this study was to describe the overall status of chemical use in the semiconductor industry in Korea and to examine it from a health perspective. Methods: Data on the status of chemical use and safety data sheets at 11 of 12 major semiconductor workplaces in Korea were collected. The number of chemical products and chemical constituents, quantities of chemicals, and trade secret ingredients used, as well as the health hazards were examined. Results: On average, 210 chemical products and 135 chemical constituents were used at the surveyed workplaces. Among all chemical products, 33% (range: 16-56%) contained at least one trade secret ingredient. Most of the trade secret ingredients were used in the photolithography process. Several carcinogens, including sulfuric acid, chromic acid, ethylene oxide, crystalline silica, potassium dichromate, and formaldehyde were also used. Only 29% (39 of 135) of the chemical constituents had occupational exposure limits, and more than 60% had no National Fire Protection Association health, safety, and reactivity ratings. Based on the aforementioned results, this study revealed the following. First, many chemical products and constituents are being used in the semiconductor industry and many products contained trade secret ingredients. Second, many products contained significant amounts of carcinogenic, mutagenic, and reproductive toxicant materials. Conclusion: We conclude that protecting workers in the semiconductor industry against harm from chemical substances will be difficult, due to widespread use of trade secret ingredients and a lack of hazard information. The findings of the status of chemical use and the health and safety risks in semiconductor industry will contribute to epidemiological studies, safe workplace, and worker health protection.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.391-392
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• 2007

In recent, portable information and communication terminals such as a notebook computer, an electronic pocketbook, a hand personal computer(PC) have been regards as the leading role in the coming next generation portable multimedia terminals which have hi-directional wireless data communication capability and can receive information and communication services such as electronic mail, database searching, and electronic shopping at anytime and anyplace. Therefore, in this paper, the circuit is simulated by 0.35um memory process used Current Limit for Boost DC-DC converter. Supply voltage $2.5V{\sim}3.3V$, output voltage 5V, Clock Frequency 1MHz, output current 200mA and line regulation decreased 12.46%.

• IE interfaces
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• v.23 no.1
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• pp.12-23
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• 2010

A semiconductor market is one of the most competitive markets in the world. To survive this competition, important targets for production planning are on-time delivery and profit maximization. In our research, we modify the linear programming model for the current production planning by adding new objective functions that maximize the profit. In addition, we propose a production planning process that gives a priority to new products, reflecting daily fluctuations in demand to weekly production planning. We validate our model with real data sets obtained from a major company semiconductor manufacturer and performed the paired t-test to verify the results. The results showed that our model forecasted profit and loss with 93.2% accuracy and improved the due date satisfaction by 10%.