• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.37 no.1
• /
• pp.43-47
• /
• 2024

The size of semiconductor devices has been scaled down to improve packing density and output performance. However, there is uncontrollable spreading of the dopants that comprise the well, punch-stop, and channel-stop when using high-temperature annealing processes, such as rapid thermal annealing (RTA). In this context, low-temperature deuterium annealing (LTDA) performed at a low temperature of 300℃ is proposed to reduce the thermal budget during CMOS fabrication. The LTDA effectively eliminates the interface trap in the gate dielectric layer, thereby improving the electrical characteristics of devices, such as threshold voltage (V_TH), subthreshold swing (SS), on-state current (I_ON), and off-state current (I_OFF). Moreover, the LTDA is perfectly compatible with CMOS processes.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2013.02a
• /
• pp.345-346
• /
• 2013

InGaN material is being studied increasingly as a prospective material for solar cells. One of the merits for solar cell applications is that the band gap energy can be engineered from 0.7 eV for InN to 3.4 eV for GaN by varying of indium composition, which covers almost of solar spectrum from UV to IR. It is essential for better cell efficiency to improve not only the crystalline quality of the epitaxial layers but also fabrication of the solar cells. Fabrication includes transparent top electrodes and surface texturing which will improve the carrier extraction. Surface texturing is one of the most employed methods to enhance the extraction efficiency in LED fabrication and can be formed on a p-GaN surface, on an N-face of GaN, and even on an indium tin oxide (ITO) layer. Surface texturing method has also been adopted in InGaN-based solar cells and proved to enhance the efficiency. Since the texturing by direct etching of p-GaN, however, was known to induce the damage and result in degraded electrical properties, texturing has been studied widely on ITO layers. However, it is important to optimize the ITO thickness in Solar Cells applications since the reflectance is fluctuated by ITO thickness variation resulting in reduced light extraction at target wavelength. ITO texturing made by wet etching or dry etching was also revealed to increased series resistance in ITO film. In this work, we report a new way of texturing by deposition of thickness-optimized ITO films on ITO nano dots, which can further reduce the reflectance as well as electrical degradation originated from the ITO etching process.

• Journal of Korean Society of Occupational and Environmental Hygiene
• /
• v.27 no.3
• /
• pp.187-192
• /
• 2017

Objectives: It is difficult to identify exposure factors in the semiconductor industry due to low exposure levels to hazardous substances and because various processes take place in fabrication (FAB). Furthermore, a single worker often experiences a variety of job histories, so it is difficult to classify similar exposure groups (SEG) in the semiconductor industry. Therefore, we intend to develop a new exposure index, the period of working in FAB, that is applicable to the semiconductor industry. Methods: First, in specifying the classification of jobs, we clearly distinguished whether they were FAB workers or non-FAB workers. We checked FAB working hours per week through questionnaires administered to FAB workers. We derived an exposure index called FAB-Year that can represent the period of working in FAB. FAB-Year is an index that can quantitatively indicate the period of working in FAB, and one FAB-Year is defined as working in FAB for 40 hours per week for one year. Results: A total of 8,453 persons were surveyed, and male engineers and female operators occupied 90% of the total. The average total years of service of the subjects was 9.7 years, and the average FAB-Year value was 6.8. This means that the FAB-working ratio occupies 70% of total years of service. The average FAB-Year value for female operators was 8.4, for male facility engineers it was 7.7, and for male process engineers it was 3.5. A FAB-Year standardization value according to personal information (gender, job group, entry year, retirement year) for the survey subjects can be calculated, and standardized estimation values can be applied to workers who are not participating in the survey, such as retirees and workers on a leave of absence (LOA). Conclusions: This study suggests an alternative method for overcoming the limitations on epidemiological study of the semiconductor industry where it is difficult to classify exposure groups by developing a new exposure index called FAB-Year. Since FAB-Year is a quantitative index, we expect that various approaches will be possible in future epidemiological studies.

• Korean Journal of Optics and Photonics
• /
• v.9 no.3
• /
• pp.191-198
• /
• 1998

A method is described to produce off-axis hologram lenses without astigmatism for semiconductor lasers. We fabricated a holographic collimating lens by using dichromated gelatin film with high diffraction efficiency and without astigmatism which makes a collimated off-axis beam of semiconductor laser. We have designed the holographic collimating lens by applying the classical ray-tracing method to holographic diffraction. The elimination of astigmatism is obtained by choosing appropriate angles of recording and reconstruction beams. The hologram is recorded by use of Ar^{+}$ laser (488nm wavelength) and reconstructed by semiconductor laser(670nm wavelength). The physical parameters of recording and reconstruction angles, wavelength, and astigmatism are analytically calculated and experimentally confirmed.

• The Transactions of the Korean Institute of Electrical Engineers
• /
• v.45 no.1
• /
• pp.113-122
• /
• 1996

As integrity of semiconductor device is increased, accurate and efficient modeling and recipe generation of semiconductor fabrication procsses are necessary. Among the major semiconductor manufacturing processes, dry etc- hing process using gas plasma and accelerated ion is widely used. The process involves a variety of the chemical and physical effects of gas and accelerated ions. Despite the increased popularity, the complex internal characteristics made efficient modeling difficult. Because of difficulty to determine the control input for the desired output, the recipe generation depends largely on experiences of the experts with several trial and error presently. In this paper, the optimal control of the etching is carried out in the following two phases. First, the optimal neural network models for etching process are developed with genetic algorithm utilizing the input and output data obtained by experiments. In the second phase, search for optimal control inputs in performed by means of using the optimal neural network developed together with genetic algorithm. The results of study indicate that the predictive capabilities of the neural network models are superior to that of the statistical models which have been widely utilized in the semiconductor factory lines. Search for optimal control inputs using genetic algorithm is proved to be efficient by experiments. (author). refs., figs., tabs.

• Transactions on Electrical and Electronic Materials
• /
• v.11 no.1
• /
• pp.15-19
• /
• 2010

In this paper, we discuss design considerations for an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) with a lateral asymmetric channel (LAC) doping profile. We employed a $0.35\;{\mu}m$ standard complementary MOSFET process for fabrication of the devices. The gates to the LAC doping overlap lengths were 0.5, 1.0, and $1.5\;{\mu}m$. The drain current ($I_{ON}$), transconductance ($g_m$), substrate current ($i_{SUB}$), drain to source leakage current ($i_{OFF}$), and channel-hot-electron (CHE) reliability characteristics were taken into account for optimum device design. The LAC devices with shorter overlap lengths demonstrated improved $I_{ON}$ and $g_m$ characteristics. On the other hand, the LAC devices with longer overlap lengths demonstrated improved CHE degradation and $I_{OFF}$ characteristics.

• Journal of the Semiconductor & Display Technology
• /
• v.22 no.4
• /
• pp.53-58
• /
• 2023

The storage capacity of 3D-NAND flash memory has been enhanced by the multi-layer dielectrics. The deposition process has become more challenging due to the tight process margin and the demand for accurate process control. To reduce product costs and ensure successful processes, process diagnosis techniques incorporating artificial intelligence (AI) have been adopted in semiconductor manufacturing. Recently there is a growing interest in process diagnosis, and numerous studies have been conducted in this field. For higher model accuracy, various process and sensor data are required, such as optical emission spectroscopy (OES), quadrupole mass spectrometer (QMS), and equipment control state. Among them, OES is usually used for plasma diagnostic. However, OES data can be distorted by viewport contamination, leading to misunderstandings in plasma diagnosis. This issue is particularly emphasized in multi-dielectric deposition processes, such as oxide and nitride (ON) stack. Thus, it is crucial to understand the potential misunderstandings related to OES data distortion due to viewport contamination. This paper explores the potential for misunderstanding OES data due to data distortion in the ON stack process. It suggests the possibility of excessively evaluating process drift through comparisons with a QMS. This understanding can be utilized to develop diagnostic models and identify the effects of viewport contamination in ON stack processes.

• Proceedings of the IEEK Conference
• /
• 2005.11a
• /
• pp.615-618
• /
• 2005

In this work, the effects of corner transistors in SOI MOSFETs were investigated. We fabricated SOI MOSFETs with various widths and a fixed length and characterized them. The SOI thickness was $4000{\AA}$ and the buried oxide(BOX) thickness was $4000{\AA}$. The isolation of active region was simply done by silicon etching and TEOS sidewall formation. Several undesirable characteristics have been reported for LOCOS isolation in fabrication on SOI wafers so far. Although we used an STI-like process instead of LOCOS, there were still a couple of abnormal phenomena such as kinks and double humps in drain current. Above all, we investigated the location of the parasitic transistors and found that they were at the corners of the SOI in width direction by high-resolution SEM inspection. It turned out that their characteristics are strongly dependent on the channel width. We made a contact pad through which we can control the body potential and figured out the dependency of operation on the body potential. The double humps became more prominent as the body bias went more negative until the full depletion of the channel where the threshold voltage shift did not occur any more. Through these works, we could get insights on the process that can reduce the effects of corner transistors in SOI MOSFETs, and several possible solutions are suggested at the end.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2007.08b
• /
• pp.1220-1224
• /
• 2007

The effects of plasma damages to the organic thin film transistor (OTFT) during the fabrication process are investigated; metal deposition process on the organic gate insulator by plasma sputtering mainly generates the process induced damages of bottom contact structured OTFTs. For this study, various deposition methods (thermal evaporation, plasma sputtering, and neutral beam based sputtering) and metals (gold and Indium-Tin Oxide) have been tested for their damage effects onto the Poly 4-vinylphenol(PVP) layer surface as an organic gate insulator. The surface damages are estimated by measuring surface energies and grain shapes of organic semiconductor on the gate insulator. Unlike thermal evaporation and neutral beam based sputtering, conventional plasma sputtering process induces serious damages onto the organic surface as increasing surface energy, decreasing grain sizes, and degrading TFT performance.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.1
• /
• pp.1-7
• /
• 2014

A bidirectional transient voltage suppression (TVS) diode consisting of specially designed $p^--n^{{+}+}-p^-$ multi-junctions was developed using low temperature (LT) epitaxy and fabrication processes. Its electrostatic discharge (ESD) performance was investigated using I-V, C-V, and various ESD tests including the human body model (HBM), machine model (MM) and IEC 61000-4-2 (IEC) analysis. The symmetrical structure with very sharp and uniform bidirectional multi-junctions yields good symmetrical I-V behavior over a wide range of operating temperature of 300 K-450 K and low capacitance as 6.9 pF at 1 MHz. In addition, a very thin and heavily doped $n^{{+}+}$ layer enabled I-V curves steep rise after breakdown without snapback phenomenon, then resulted in small dynamic resistance as $0.2{\Omega}$, and leakage current completely suppressed down to pA. Manufactured bidirectional TVS diodes were capable of withstanding ${\pm}4.0$ kV of MM and ${\pm}14$ kV of IEC, and exceeding ${\pm}8$ kV of HBM, while maintaining reliable I-V characteristics. Such an excellent ESD performance of low capacitance and dynamic resistance is attributed to the abruptness and very unique profiles designed very precisely in $p^--n^{{+}+}-p^-$ multi-junctions.