• 제목/요약/키워드: Semiconductor Fabrication

검색결과 948건 처리시간 0.028초

A 32 by 32 Electroplated Metallic Micromirror Array

  • Lee, Jeong-Bong
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제2권4호
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    • pp.288-294
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    • 2002
  • This paper presents the design, fabrication and characterization of a 32 by 32 electroplated micromirror array on a glass, a low cost substrate. Approaches taken in this work for the fabrication of micromachined mirror arrays include a line addressing scheme, a seamless array design for high fill factor, planarization techniques of polymeric interlayers, a high yield methodology for the removal of sacrificial polymeric interlayers, and low temperature and chemically safe fabrication techniques. The micromirror is fabricated by aluminum and the size of a single micromirror is 200 $\mu\textrm{m}{\;}{\times}200{\;}\mu\textrm{m}$. Static deflection test of the micro-mirror has been carried out and pull-in voltage of 44V and releasing voltage of 30V was found.

마이크로 파워 시스템의 개발 (Micro Power System Development)

  • 박건중;전병선;민홍석;송성진;민경덕;주영창
    • 유체기계공업학회:학술대회논문집
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    • 유체기계공업학회 2001년도 유체기계 연구개발 발표회 논문집
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    • pp.381-386
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    • 2001
  • This paper reports on the development of micro power system under way at Seoul National University. The interdisciplinary tin consists of members with various backgrounds of mechanics and materials. The need for micro power systems is explained, and a turbine under development is described. Design, and fabrication are introduced, and technical challenges in each phase are described. Furthermore, the interaction between the available fabrication methods and design is explained. Design involves use of commercially available codes to analyze flow fields, and fabrication takes advantage of the silicon wafer etching processes used to manufacture semiconductor devices.

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실리콘 에피층 성장과 실리콘 에칭기술을 이용한 Bare Chip Burn-In 테스트용 인터컨넥션 시스템의 제조공정 (Fabrication Processes of Interconnection Systems for Bare Chip Burn-In Tests Using Epitaxial Layer Growth and Etching Techniques of Silicon)

  • 권오경;김준배
    • 한국표면공학회지
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    • 제28권3호
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    • pp.174-181
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    • 1995
  • Multilayered silicon cantilever beams as interconnection systems for bare chip burn-in socket applications have been designed, fabricated and characterized. Fabrication processes of the beam are employing standard semiconductor processes such as thin film processes and epitaxial layer growth and silicon wet etching techniques. We investigated silicon etch rate in 1-3-10 etchant as functions of doping concentration, surface mechanical stress and crystal defects. The experimental results indicate that silicon etch rate in 1-3-10 etchant is strong functions of doping concentration and crystal defect density rather than surface mechanical stress. We suggested the new fabrication processes of multilayered silicon cantilever beams.

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Research Infrastructure Foundation for Core-technology Incubation of Radiation Detection System

  • Kim, Han Soo;Ha, Jang Ho;Kim, Young Soo;Cha, Hyung Ki
    • 방사선산업학회지
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    • 제6권1호
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    • pp.67-73
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    • 2012
  • The development of radiation detection systems mainly consist of two parts-radiation detector fabrication including material development, and its appropriate electronics development. For the core-technology incubation of a radiation detection system, radiation fabrication and an evaluation facility are scheduled to be founded at the RFT (Radiation Fusion Technology) Center at KAERI (Korea Atomic Energy Research Institute) by 2015. This facility is utilized for the development and incubation of bottleneck-technologies to accelerate the industrialization of a radiation detection system in the industrial, medical, and radiation security fields. This facility is also utilized for researchers to develop next-generation radiation detection instruments. In this paper, the establishment of core-technology development is introduced and its technological mission is addressed.

p-Si 기판 위에 형성된 $S iO_2/S iN/S iO_2$박막의 특성에 관한 연구 (fabrication and characterization of $S iO_2/S iN/S iO_2$ films on p-Si)

  • 성규석;이세준;김두수;강윤묵;차정호;김현정;정웅;김득영;홍치유;조훈영;강태원
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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    • pp.32-35
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    • 2000
  • Oxide-nitride-oxide(ONO) structures were formed by sequential radio frequency reactive magnetron sputtering method. The chemical composition and structure of these films were studied by using of secondary ion mass spectroscopy(SIMS) and Auger electron spectroscopy(AES) SIMS and AES experiments show the existence of nitridation at the SiO$_2$/Si substrate. The electrical characteristics of ONO films were evaluated by I-V and high frequency C-V measurements When the ONO films were annealed at 90$0^{\circ}C$ for 30 sec in $N_2$ ambient, the breakdown voltage increased and flat-band voltage decreased under high electric field.

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Fabrication and Electrical Properties of Local Damascene FinFET Cell Array in Sub-60nm Feature Sized DRAM

  • Kim, Yong-Sung;Shin, Soo-Ho;Han, Sung-Hee;Yang, Seung-Chul;Sung, Joon-Ho;Lee, Dong-Jun;Lee, Jin-Woo;Chung, Tae-Young
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제6권2호
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    • pp.61-67
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    • 2006
  • We fabricate local damascene FinFET cell array in sub-60nm feature sized DRAM. The local damascene structure can remove passing-gate-effects in FinFET cell array. p+ boron in-situ doped polysilicon is chosen for the gate material, and we obtain a uniform distribution of threshold voltages at around 0.7V. Sub-threshold swing of 75mV/d and extrapolated off-state leakage current of 0.03fA are obtained, which are much suppressed values against those of recessed channel array transistors. We also obtain a few times higher on-state current. Based on the improved on- and off-state current characteristics, we expect that the FinFET cell array could be a new mainstream structure in sub-60nm DRAM devices, satisfying high density, low power, and high-speed device requirements.

SiGe/Si 이종접합구조의 채널을 이용한 SOI n-MOSFET의 DC 특성 (DC Characteristic of Silicon-on-Insulator n-MOSFET with SiGe/Si Heterostructure Channel)

  • 최아람;최상식;양현덕;김상훈;이상흥;심규환
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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    • pp.99-100
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    • 2006
  • Silicon-on-insulator(SOI) MOSFET with SiGe/Si heterostructure channel is an attractive device due to its potent use for relaxing several limits of CMOS scaling, as well as because of high electron and hole mobility and low power dissipation operation and compatibility with Si CMOS standard processing. SOI technology is known as a possible solution for the problems of premature drain breakdown, hot carrier effects, and threshold voltage roll-off issues in sub-deca nano-scale devices. For the forthcoming generations, the combination of SiGe heterostructures and SOI can be the optimum structure, so that we have developed SOI n-MOSFETs with SiGe/Si heterostructure channel grown by reduced pressure chemical vapor deposition. The SOI n-MOSFETs with a SiGe/Si heterostructure are presented and their DC characteristics are discussed in terms of device structure and fabrication technology.

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RIE 공정을 이용한 유기발광다이오드의 광 산란층 제작 (Fabrication of Scattering Layer for Light Extraction Efficiency of OLEDs)

  • 배은정;장은비;최근수;서가은;장승미;박영욱
    • 반도체디스플레이기술학회지
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    • 제21권1호
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    • pp.95-102
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    • 2022
  • Since the organic light-emitting diodes (OLEDs) have been widely investigated as next-generation displays, it has been successfully commercialized as a flexible and rollable display. However, there is still wide room and demand to improve the device characteristics such as power efficiency and lifetime. To solve this issue, there has been a wide research effort, and among them, the internal and the external light extraction techniques have been attracted in this research field by its fascinating characteristic of material independence. In this study, a micro-nano composite structured external light extraction layer was demonstrated. A reactive ion etching (RIE) process was performed on the surfaces of hexagonally packed hemisphere micro-lens array (MLA) and randomly distributed sphere diffusing films to form micro-nano composite structures. Random nanostructures of different sizes were fabricated by controlling the processing time of the O2 / CHF3 plasma. The fabricated device using a micro-nano composite external light extraction layer showed 1.38X improved external quantum efficiency compared to the reference device. The results prove that the external light extraction efficiency is improved by applying the micro-nano composite structure on conventional MLA fabricated through a simple process.

구조개질 Apatite의 항균효과 (The Antimicrobial Effect of Structure Modified Apatite)

  • 강전택;정기호
    • 한국환경과학회지
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    • 제10권6호
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    • pp.387-391
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    • 2001
  • The hydroxyapatite(HAp) as a carrier the for ion exchange agent of $Ag^+$ions was prepared in semiconductor fabrication, The Ca/P molar ratio of the HAp was 1.65. The HAp is molded in shape of the antimcrobial ball and then sintered at 100$0^{\circ}C$ Ag-containing HAp(HAp-Ag) was prepared by incorporating $Ag^+$/ions in HAp crystals through an ion-exchange reaction in solutions containing 0.01M $AgNO_3$. The antimicrobial effect of HAp-Ag for bacteria such as Escherichial coli and Staphylococcus aureus has been Investigated. The concentrations of silver in the antimicrobial ball was determined by inductively coupled plasma and the amount of $Ag^+$ions was 9.0$\mu\textrm{g}$/g. The HAp-Ag exhibited excellent antimicrobial effect for bacteria such as E. coli and S. aureus. The bactericidal activity was considered to be caused by direct contact of bacteria with $Ag^+$ions in the HAp crystals. The HAp would likely to be possible as a carrier of antimicrobial metal ions such as Ag, Cu, and Zn by recycling of waste sludge in the semiconductor fabrication process.

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InGaZnO 용액의 농도가 Drop-casting으로 제작된 산화물 박막 트랜지스터의 전기적 특성에 미치는 영향 (Effect of InGaZnO Solution Concentration on the Electrical Properties of Drop-Cast Oxide Thin-Film Transistors)

  • 노은경;유경민;김민회
    • 센서학회지
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    • 제29권5호
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    • pp.332-335
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    • 2020
  • Drop casting, a solution process, is a simple low-cost fabrication technique that does not waste material. In this study, we elucidate the effect of the concentration of a InGaZnO solution on the electrical properties of drop-cast oxide thin-film transistors. The higher the concentration the larger the amount of remnant InGaZnO solutes, which yields a thicker thin film. Accordingly, the electrical properties were strongly dependent on the concentration. At a high concentration of 0.3 M (or higher), a large current flowed but did not lead to switching characteristics. At a concentration lower than 0.01 M, switching characteristics were observed, but the mobility was small. In addition to a high mobility, sufficient switching characteristics were obtained at a concentration of 0.1 M owing to the appropriate thickness of the semiconductor layer. This study provides a technical basis for the low-cost fabrication of switching devices capable of driving a sensor array.