• Design & Manufacturing
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• 제2권6호
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• pp.11-16
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• 2008

In order to satisfy the customer's variant needs for a product quality in recent years, a demand for developing higher precision machining technologies in a lot of application areas such as automobile, cellular phone and semiconductor has been increased more and more. Micro-magnetic induced polishing(${\mu}-MIP$) process is one of these precision technologies. In this study, to verify the parameters' effect of the ${\mu}-MIP$ process on the surface roughness improvement of the inclined workpiece, well planned experiment which was called the design of experiments was carried out. Considered parameters were spindle speed, inductor current, abrasive configuration and working gap between the workpiece and the solid tool. As a result, it was seen that the inductor current and the working gap greatly affected the surface roughness improvement. And to predict the surface roughness of the inclined workpiece, S/N ratio and first-order response surface model was developed.

• Journal of Mechanical Science and Technology
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• 제19권4호
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• pp.968-975
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• 2005

The shearing process for the sheet metal is normally used in the precision elements such as semi-conductor components. In these precision elements, the burr formation brings a bad effect on the system assembly and demands the additional de-burring process, so this imposes high cost on manufacturing. In this paper, we have developed the in-situ auto-aligning precision meso-punching system to investigate the burr formation mechanism and ultimately minimize burr. Firstly, we introduced the punch-die contact sensing method to align the punch and the die at initial state prior to the punching process. Secondly, by using the low-price semi-con­ductor laser, burr formed on the edges is measured intermittently during the punching process. We could, finally, make burr on the sheet metal uniformized and minimized by controlling of the precision X - Y table, $1\;{\mu}m$ resolution, and measuring burr height by semiconductor laser. Experimental results show the validity of our system for pursuing the burr-free punched elements.

• Design & Manufacturing
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• 제14권1호
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• pp.36-41
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• 2020

Recently, due to the development of MEMS technology, researches for the production of effective micro structures and shapes have been actively conducted. However, the process technology based on chemical etching has a number of problems such as environmental pollution and time problems due to multi-process. Various processes to cope with this process are being studied, and one of the mechanical etching processes is the powder blasting process. This process is a method of spraying fine particles, which has the advantage of being an effective process in manufacturing hard brittle materials. However, it is also a process that adversely affects the material surface roughness and material properties due to the impact of the injection of fine particles. In this study, after fabricating micro-channels in fused silica glass with excellent optical properties among the hard brittle materials, we used the nano indentation system to analyze the micro parts using nano-particles as well as machinability and surface roughness analysis of the processed surface. The analysis was performed for the effective processing of powder blasting.

• Journal of Welding and Joining
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• 제32권3호
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• pp.11-18
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• 2014

TSV(through silicon via) filling technology is making a hole in Si wafer and electrically connecting technique between front and back of Si die by filling with conductive metal. This technology allows that a three-dimensionally connected Si die can make without a large number of wire-bonding. These TSV technologies require various engineering skills such as forming a via hole, forming a functional thin film, filling a conductive metal, polishing a wafer, chip stacking and TSV reliability analysis. This paper addresses the TSV filling using Cu electrodeposition. The impact of plating conditions with additives and current density on electrodeposition will be considered. There are additives such as accelerator, inhibitor, leveler, etc. suitably controlling the amount of the additive is important. Also, in order to fill conductive material in whole TSV hole, current wave forms such as PR(pulse reverse), PPR(periodic pulse reverse) are used. This study about semiconductor packaging will be able to contribute to the commercialization of 3D TSV technology.

• 마이크로전자및패키징학회지
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• 제14권1호
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• pp.19-26
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• 2007

본 연구의 목적은 CMOS 이미지 센서용 Au 플립칩 범프와 전해 도금된 Au 기판 사이의 초음파 접합의 가능성 연구이다. 초음파 접합 조건을 최적화하기 위해서, 대기압 플라즈마 세정 후 접합 압력과 시간을 달리하여 초음파 접합 후 전단 시험을 실시하였다. 범프의 접합 강도는 접합 압력과 시간 변수에 크게 좌우되었다. Au 플립칩 범프는 상온에서 성공적으로 하부 Au 도금 기판과 접합되었으며, 최적 조건 하에서 접합 강도는 약 73 MPa이었다.

• ETRI Journal
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• 제36권6호
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• pp.931-941
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• 2014

Many methodologies for clock mesh networks have been introduced for two-dimensional integrated circuit clock distribution networks, such as methods to reduce the total wirelength for power consumption and to reduce the clock skew variation through consideration of buffer placement and sizing. In this paper, we present a methodology for clock mesh to reduce both the clock skew and the total wirelength in three-dimensional integrated circuits. To reduce the total wirelength, we construct a smaller mesh size on a die where the clock source is not directly connected. We also insert through-silicon vias (TSVs) to distribute the clock signal using an effective clock TSV insertion algorithm, which can reduce the total wirelength on each die. The results of our proposed methods show that the total wirelength was reduced by 12.2%, the clock skew by 16.11%, and the clock skew variation by 11.74%, on average. These advantages are possible through increasing the buffer area by 2.49% on the benchmark circuits.

• Design & Manufacturing
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• 제10권2호
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• pp.50-54
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• 2016

In the semiconductor industry the final products were checked for several environments before sell the products. The burning test of memory and chip was implemented in reliability for all of parts. The memory and chip were developed to high density memory and high performance chip, so circuit design was also high integrated and the test bed was needed to be thin and fine pitch socket. LGA(Land Grid Array) IC socket with thin wall thickness was designed to satisfy this requirement. The LGA IC socket plastic part was manufacture by injection molding process, it was needed accuracy, stiffness and suit resin with high flowability. In this study, injection molding process analysis was executed for 2 and 4 cavities moldings with runner, gate and sprue. The warpage analysis was also implemented for further gate removal process. Through the analyses the total deformations of the moldings were predicted within maximum 0.05mm deformation. Finally in consideration of these results, 2 and 4 cavities molds were designed and made and tested in injection molding process.

• 한국정밀공학회지
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• 제11권1호
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• pp.150-156
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• 1994

To meet the process requirement of semiconductor device manufacturing, it is necessary to improve the alignment accuracy in exposure equipments. We developed the excimer laser stepper and will describe the methodology for alignment measurement and experimental results. Our wafer alignment system consists of off-axis optics, TTL(Through The Lens) optics and high precision stage. Off-axis alignment utilizes the image processing and /or diffraction from thealign marks of off-centered chip area. On the other hand, TTL alignment can be used for the die-by-die alignment using dual beam interferometry. When only off-axis alignment was used, the experimental alignment error(lml+3 .sigma. ) was 0.26-0.29 .mu. m, and will be reduced down to 0.15 .mu. m by adding TTL alignment.

• Design & Manufacturing
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• 제7권1호
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• pp.55-59
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• 2013

A Light Emitting Diode(LED) is a semiconductor device which converts electricity into light. LEDs are widely used in a field of illumination, LCD(Liquid Crystal Display) backlight, mobile signals because they have several merits, such as low power consumption, long lifetime, high brightness, fast response, environment friendly. In general, LEDs production does die bonding and wire bonding on board, and do silicon and phosphor dispensing to protect LED chip and improve brightness. Then lens molding process is performed using mixed liquid silicon rubber(LSR) by resin and hardener. A mixture of resin and hardener affect the optical characteristics of the LED lens. In this paper, computational design of static mixer was performed for mixing of liquid silicon. To evaluate characteristic of mixing efficiency, finite element model of static mixer was generated, and fluidic analysis was performed according to length of mixing element. Finally, optimal condition of length of mixing element was applied to static mixer from result of fluidic analysis.

• 마이크로전자및패키징학회지
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• 제20권3호
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• pp.31-35
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• 2013

TSOP(Thin Small Outline Package)는 가전제품, 자동차, 모바일, 데스크톱 PC등을 위한 저렴한 비용의 패키지로, 리드 프레임을 사용하는 IC패키지이다. TSOP는 BGA와 flip-chip CSP에 비해 우수한 성능은 아니지만, 저렴한 가격 때문에 많은 분야에 널리 사용되고 있습니다. 그러나, TSOP 패키지에서 몰딩공정 할 때 리드프레임의 열적 처짐 현상이 빈번하게 일어나고, 반도체 다이와 패드 사이의 Au 와이어 떨어짐 현상이 이슈가 되고 있다. 이러한 문제점을 해결하기 위해서는 리드프레임의 구조를 개선하고 낮은 CTE를 갖는 재료로 대체해야 한다. 본 연구에서는 열적 안정성을 갖도록 리드프레임 구조 개선을 위해 수치해석적 방법으로 진행하였다. TSOP 패키지에서 리드프레임의 열적 처짐은 반도체와 다이 사이의 거리(198 um~366 um)에서 안티-디플렉션의 위치에 따라 시뮬레이션을 진행하였다. 안티-디플렉션으로 TSOP 패키지의 열적 처짐은 확실히 개선되는 것을 확인 했다. 안티-디플렉션의 위치가 inside(198 um)일 때 30.738 um 처짐을 보였다. 이러한 결과는 리드프레임의 열적 팽창을 제한하는데 안티-디플렉션이 기여하고 있기 때문이다. 그러므로 리드프레임 패키지에 안티-디플렉션을 적용하게 되면 낮은 CTE를 갖는 재료로 대체하지 않아도 열적 처짐을 향상시킬 수 있음을 기대할 수 있다.