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Numerical Analysis for Thermal-deformation Improvement in TSOP(Thin Small Outline Package) by Anti-deflection Adhesives

TSOP(Thin Small Outline Package) 열변형 개선을 위한 전산모사 분석

  • Kim, Sang-Woo (Rare metal R&D Group, Korea institute of Industrial Technology) ;
  • Lee, Hai-Joong (Rare metal R&D Group, Korea institute of Industrial Technology) ;
  • Lee, Hyo-Soo (Rare metal R&D Group, Korea institute of Industrial Technology)
  • Received : 2013.06.03
  • Accepted : 2013.07.03
  • Published : 2013.09.30

Abstract

TSOP(Thin Small Outline Package) is the IC package using lead frame, which is the type of low cost package for white electronics, auto mobile, desktop PC, and so on. Its performance is not excellent compared to BGA or flip-chip CSP, but it has been used mostly because of low price of TSOP package. However, it has been issued in TSOP package that thermal deflection of lead frame occurs frequently during molding process and Au wire between semiconductor die and pad is debonded. It has been required to solve this problem through substituting materials with low CTE and improving structure of lead frame. We focused on developing the lead frame structure having thermal stability, which was carried out by numerical analysis in this study. Thermal deflection of lead frame in TSOP package was simulated with positions of anti-deflection adhesives, which was ranging 198 um~366 um from semiconductor die. It was definitely understood that thermal deflection of TSOP package with anti-deflection adhesives was improved as 30.738 um in the case of inside(198 um), which was compared to that of the conventional TSOP package. This result is caused by that the anti-deflection adhesives is contributed to restrict thermal expansion of lead frame. Therefore, it is expected that the anti-deflection adhesives can be applied to lead frame packages and enhance their thermal deflection without any change of substitutive materials with low CTE.

TSOP(Thin Small Outline Package)는 가전제품, 자동차, 모바일, 데스크톱 PC등을 위한 저렴한 비용의 패키지로, 리드 프레임을 사용하는 IC패키지이다. TSOP는 BGA와 flip-chip CSP에 비해 우수한 성능은 아니지만, 저렴한 가격 때문에 많은 분야에 널리 사용되고 있습니다. 그러나, TSOP 패키지에서 몰딩공정 할 때 리드프레임의 열적 처짐 현상이 빈번하게 일어나고, 반도체 다이와 패드 사이의 Au 와이어 떨어짐 현상이 이슈가 되고 있다. 이러한 문제점을 해결하기 위해서는 리드프레임의 구조를 개선하고 낮은 CTE를 갖는 재료로 대체해야 한다. 본 연구에서는 열적 안정성을 갖도록 리드프레임 구조 개선을 위해 수치해석적 방법으로 진행하였다. TSOP 패키지에서 리드프레임의 열적 처짐은 반도체와 다이 사이의 거리(198 um~366 um)에서 안티-디플렉션의 위치에 따라 시뮬레이션을 진행하였다. 안티-디플렉션으로 TSOP 패키지의 열적 처짐은 확실히 개선되는 것을 확인 했다. 안티-디플렉션의 위치가 inside(198 um)일 때 30.738 um 처짐을 보였다. 이러한 결과는 리드프레임의 열적 팽창을 제한하는데 안티-디플렉션이 기여하고 있기 때문이다. 그러므로 리드프레임 패키지에 안티-디플렉션을 적용하게 되면 낮은 CTE를 갖는 재료로 대체하지 않아도 열적 처짐을 향상시킬 수 있음을 기대할 수 있다.

Keywords

References

  1. J. H. Lau, Low Cost Flip Chip Technology, pp.1-90, McGraw Hill, New York (2001).
  2. J. H. Lau, Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies, pp.1-408, McGraw Hill, New York (1997).
  3. H. Ye, C. Basaran and D. C. Hopkins, "Damage Mechanics of Microelectronics Solder Joints under High Current Densities", Int. J. Solids Structures, 40, 4021 (2003). https://doi.org/10.1016/S0020-7683(03)00175-6
  4. D. G. Kim, J. W. Kim, J. G. Lee, H. Mori, D. J. Quesnel and S. B. Jung, "Solid State Interfacial Reaction and Joint Strength of Sn-37Pb Solder with Ni-P Under Bump Metallization in Flip Chip Application", J. Alloys Compd., 395, 80 (2005). https://doi.org/10.1016/j.jallcom.2004.11.038
  5. J. W. Yoon, W. C. Moon and S. B. Jung, "Core Technology of Electronic Packaging", Journal of KWS, 23(2), 116 (2005).
  6. J. E. Galloway and B. M. Miles, "Moisture Absorption and Desorption Predictions for Plastic Ball Grid Array Package", IEEE Trans. Comp., Packag., Manufact. Technol. A, 20(3), 274 (1997). https://doi.org/10.1109/95.623021
  7. W. -L. Yang and D. M. S. Yin, "The Effects of Epoxy Molding Composition on the Warpage and Popcorn Resistance of PBGA", Proc. 49th ECTC, San Diego, 721, IEEE CPMT/EIA (1999).
  8. S. Cho, H. Jung and O. Bae, "Numerical Analysis on the Design Variables and Thickness Deviation Effects on Warpage of Substrate for FCCSP" J. Microelectron. Packag. Soc., 19(3), 57 (2012).
  9. S. H. Hwang, B. J. Kim, S. Y. Jung, H. Y. Lee and Y. C. Joo, "Thermo-Mechanical Analysis of Though-Silicon-Via in 3D Packaging", J. Microelectron. Packag. Soc., 17(1), 69 (2010).
  10. T. K. Lee, D. M. Kim, H. I. Jun, S. W. Ha and M. Y. Jeong, "The Optimization of FCBGA Thermal Design by Micro Pattern Structure", J. Microelectron. Packag. Soc., 18(3), 59 (2011).