• Journal of the Optical Society of Korea
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• 제5권1호
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• pp.5-8
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• 2001

In this work, we studied the effect of chirped grating on optical bistability in λ/4-shifted semiconductor distributed-feedback(DFB) devices, such as an etalon with nonlinear mirrors, a λ/4-shifted DFB waveguide and aλ/4-shifted DFB laser amplifier. We found that chirped DFB devices exhibit bistable switching at a lower input power.OCIS code : 050.2770, 190.1450, 190.5970, 230.0230.

• 한국반도체및디스플레이장비학회:학술대회논문집
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• 한국반도체및디스플레이장비학회 2005년도 춘계 학술대회
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• pp.134-138
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• 2005

Recently many researches related with biotechnology are processed and it is the situation that research about micro fluidic devices is active. Micro fluidic devices has been one of the most widely used devices for the analysis in biotechnology because they have many advantages, flexibility, transparency, thermal and electrical stability, nontoxic, etc. In this study, micro fluidic device with PDMS is developed for particle counter which separates a small quantity of particles, The principle of micro particle counter is electrical-impedance method, and it was also applied hydrodynamic flow focusing. It is more efficient method to analyzing particles furthermore it can be applied to cell count ins for biotechnology.

• 반도체디스플레이기술학회지
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• 제3권4호
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• pp.29-32
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• 2004

Fully depleted Silicon-on-Insulator (FD-SOI) devices lead to better electrical characteristics than bulk CMOS devices. However, the presence of a thin top silicon layer and a buried SiO2 layer causes self-heating due to the low thermal conductivity of the buried oxide. The electrical characteristics of FDSOI devices strongly depend on the path of heat dissipation. In this paper, we present a new three-dimensional (3-D) analysis technique for the self-heating effect of the finger-type and bar-type transistors. The 3-D analysis results show that the drain current of the finger-type transistor is 14.7% smaller than that of the bar-type transistor due to the 3-D self-heating effect. We have learned that the rate of current degradation increases significantly when the width of a transistor is smaller that a critical value in a finger-type layout. The current degradation fro the 3-D structures of the finger-type and bar-type transistors is investigated and the design issues are also discussed.

• 반도체디스플레이기술학회지
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• 제18권2호
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• pp.1-5
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• 2019

As the number of IOT devices is growing rapidly, various 'see-thru connection' techniques have been reported for efficient communication with them. In this paper, we propose a deep learning based IOT device recognition system for interaction with these devices. The overall system consists of a TensorFlow based deep learning server and two Android apps for data collection and recognition purposes. As the basic neural network model, we adopted Google's inception-v3, and modified the output stage to classify 20 types of IOT devices. After creating a data set consisting of 1000 images of 20 categories, we trained our deep learning network using a transfer learning technology. As a result of the experiment, we achieve 94.5% top-1 accuracy and 98.1% top-2 accuracy.

• 반도체디스플레이기술학회지
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• 제17권4호
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• pp.6-10
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• 2018

Organic light emitting devices have attracted the attention of many people because of their high potential for self-emission and flexible display devices. However, due to limitations in device efficiency and lifetime, partial commercialization is underway. In this paper, we have investigated the electrical conduction mechanism of the organic light emitting device by the temperature and the thickness of the light emitting layer through the current - voltage characteristics with respect to the conduction mechanism directly affecting the efficiency and lifetime of the organic light emitting device. Through the study, it was found that the conduction in the low electric field region is caused by the movement of the heat excited charge in the ohmic region and the tunneling of the electric charge due to the high electric field in the high electric field region.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권3호
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• pp.360-369
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• 2012

The causes of showing different subthreshold slopes (SS) in programmed and erased states for two different charge trap flash (CTF) memory devices, SONOS type flash memory with gate-all-around (GAA) structure and TANOS type NAND flash memory with planar structure were investigated. To analyze the difference in SSs, TCAD simulation and low-frequency noise (LFN) measurement were fulfilled. The device simulation was performed to compare SSs considering the gate electric field effect to the channel and to check the localized trapped charge distribution effect in nitride layer while the comparison of noise power spectrum was carried out to inspect the generation of interface traps ($N_{IT}$). When each cell in the measured two memory devices is erased, the normalized LFN power is increased by one order of magnitude, which is attributed to the generation of $N_{IT}$ originated by the movement of hydrogen species ($h^*$) from the interface. As a result, the SS is degraded for the GAA SONOS memory device when erased where the $N_{IT}$ generation is a prominent factor. However, the TANOS memory cell is relatively immune to the SS degradation effect induced by the generated $N_{IT}$.

• 한국통신학회논문지
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• 제16권7호
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• pp.615-627
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• 1991

In this paper the relative magnitudes of the 1/f noise constants were experimentally investigated in the plana type's resistors fabricated with the different type's semicondector materials, and a new measurement technique for the 1/f noise in the semiconductor plana type's resistors may be located at the semiconductor and silicon dioxde.

• E2M - 전기 전자와 첨단 소재
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• 제4권2호
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• pp.159-174
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• 1991

이중주입효과에 의한 고내압 반도체 스위칭소자의 설계 제작에 촛점을 맞추어 Injection Gate구조와 MOS Gate 구조로 시료소자를 제작해 그 특성을 검토하고 Electrical Switching 및 Oxide막에서의 Breakdown현상에 의한 문제점을 해결해 보고자 Optical Gate구조를 제안하여 이 optically Gated Semiconductor Switching 소자의 동작특성을 연구하고 Injection Gate 구조를 제안하여 이 optically Gated Semiconductor Switching 소자의 동작특성을 연구하고 Injection Gate 및 MOS Gate 구조(Planar type, V-Groove type, Injection Gate mode, Optical Gate mode)로 설계제작된 소자와 특성을 비교 분석하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권3호
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• pp.153-166
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• 2003

Failure analysis is fundamental to the design and development methodology of electrostatic discharge (ESD) devices and ESD robust circuits. The role of failure analysis (FA) in the models, methodology, band mechanisms evaluation for improving ESD robustness of semiconductor products in CMOS, silicon-on-insulator (SOI) and silicon germanium (SiGe) technologies will be reviewed.

• 반도체디스플레이기술학회지
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• 제6권2호
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• pp.45-48
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• 2007

The proposed method offers an improved DC/DC converter scheme to increase power density. It is based on half-bridge topology with newly introduced pulse-grouping control method, which helps to reduce the transformer size and the volume of semiconductor devices maintaining high efficiency. Test results with 85W(18.5V/4.6A) design shows that the measured efficiency is 93.5% with power density of $36W/in^3$.