• JSTS:Journal of Semiconductor Technology and Science
• /
• 제16권4호
• /
• pp.470-480
• /
• 2016

The reversal of a silicon chip to find out its security structure is common and possible at the present time. Thanks to reversing, it is possible to use a probing attack to obtain useful information such as personal information or a cryptographic key. For this reason, security-related blocks such as DES (Data Encryption Standard), AES (Advanced Encryption Standard), and RSA (Rivest Shamir Adleman) engines should be located in the lower layer of the chip to guard against a probing attack; in this regard, the addition of a silicon-surface-protection layer onto the chip surface is a crucial protective measure. But, for manufacturers, the implementation of an additional silicon layer is burdensome, because the addition of just one layer to a chip significantly increases the overall production cost; furthermore, the chip size is increased due to the bulk of the secure logic part and routing area of the silicon protection layer. To resolve this issue, this paper proposes a practical silicon-surface-protection method using a metal layer that increases the security level of the chip while minimizing its size and cost. The proposed method uses a shift register for the alternation and variation of the metal-layer data, and the inter-connection area is removed to minimize the size and cost of the chip in a more extensive manner than related methods.

• 정보보호학회논문지
• /
• 제12권4호
• /
• pp.87-98
• /
• 2002

현재는 유형적인 물질의 가치보다 무형적인 정보의 가치가 중요시되고 있는 시대이다. 특히 하드웨어보다는 소프트웨어 제품이 훨씬 급성장하고 있지만 소프트웨어 불법 복제는 정보화시대의 가장 큰 역기능으로 이슈화 되어있다. 그러나 현재 상용화되고 있는 소프트웨어 불법복제방지제품(락)들은 복제방지에 대한 강도가 약하기 때문에 쉽게 락이 크랙되어 복제방지 기능을 할 수 없는 것들이 대부분이다. 논자는 [1,2,3]에서 DES 암호알고리즘을 대체 할 수 있는 112비트 키 길이를 갖는 96비트 블록 Cipher를 제안한 바 있으며, [3.4]에서 칩으로 하였다. 따라서 본 논문은 [1,2,3]에서 제안한 96비트 블록 Cipher와 복제방지에 필요한 보안모듈을 ASIC화하여 소프트웨어 복제방지를 위한 전용 보안칩을 설계 및 구현하며, 보안칩과 연동하여 동작되는 자동블록보호기법을 설계한다.

• 한국정보보호학회:학술대회논문집
• /
• 한국정보보호학회 1994년도 종합학술발표회논문집
• /
• pp.193-202
• /
• 1994

In this paper, we investigate possible scrambling methods for the JPEG(Joint Photographic Export Group) still image compression standard. In particular, we compare the conventional line rotation and line permutation methods to the DCT block scrambling in terms of the number of bits to be increased and the easiness of buffer control. Computer simulation results show that the DCT block scrambling method is suitable for both data security and buffer control in one-chip JPEG applications.

• Nuclear Engineering and Technology
• /
• 제53권10호
• /
• pp.3327-3334
• /
• 2021

Present electric grids are advanced to integrate smart grids, distributed resources, high-speed sensing and control, and other advanced metering technologies. Cybersecurity is one of the challenges of the smart grid and nuclear plant digital system. It affects the advanced metering infrastructure (AMI), for grid data communication and controls the information in real-time. The research article is emphasized solving the nuclear and smart grid hardware security issues with the integration of field programmable gate array (FPGA), and implementing the latest Time Authenticated Cryptographic Identity Transmission (TACIT) cryptographic algorithm in the chip. The cryptographic-based encryption and decryption approach can be used for a smart grid distribution system embedding with FPGA hardware. The chip design is carried in Xilinx ISE 14.7 and synthesized on Virtex-5 FPGA hardware. The state of the art of work is that the algorithm is implemented on FPGA hardware that provides the scalable design with different key sizes, and its integration enhances the grid hardware security and switching. It has been reported by similar state-of-the-art approaches, that the algorithm was limited in software, not implemented in a hardware chip. The main finding of the research work is that the design predicts the utilization of hardware parameters such as slices, LUTs, flip-flops, memory, input/output blocks, and timing information for Virtex-5 FPGA synthesis before the chip fabrication. The information is extracted for 8-bit to 128-bit key and grid data with initial parameters. TACIT security chip supports 400 MHz frequency for 128-bit key. The research work is an effort to provide the solution for the industries working towards embedded hardware security for the smart grid, power plants, and nuclear applications.

• 한국전기전자재료학회논문지
• /
• 제37권5호
• /
• pp.527-532
• /
• 2024

Physically Unclonable Functions (PUFs) provide a high level of security for private keys using unique physical characteristics of hardware. However, fabricating PUF chips requires numerous semiconductor processes, leading to high costs, which limits their applications. In this work, we introduce a low-cost manufacturing method for PUF security chips. First, surface roughening through wet-etching is utilized to create random variables. Additionally, physical vapor deposition is added to further enhance randomness. After PUF chip fabrication, both Hamming distance (HD) and Hamming weight (HW) are extracted and compared to verify the fabricated chip. It is confirmed that the PUF chip using two different multiple process variables demonstrates superior uniqueness and uniformity compared to the PUF security chip fabricated using only a single process variable.

• 전기학회논문지P
• /
• 제67권1호
• /
• pp.9-14
• /
• 2018

In this paper, we introduce an AES-based security chip for the embedded system of Internet of Things(IoT). We used Verilog HDL to implement the AES algorithm in FPGA. The designed AES module creates 128-bit cipher by encrypting 128-bit plain text and vice versa. RTL simulations are performed to verify the AES function and the theory is compared to the results. An FPGA emulation was also performed with 40 types of test sequences using two Altera DE0-Nano-SoC boards. To evaluate the performance of security algorithms, we compared them with AES implemented by software. The processing cycle per data unit of hardware implementation is 3.9 to 7.7 times faster than software implementation. However, there is a possibility that the processing speed grow slower due to the feature of the hardware design. This can be solved by using a pipelined scheme that divides the propagation delay time or by using an ASIC design method. In addition to the AES algorithm designed in this paper, various algorithms such as IPSec can be implemented in hardware. If hardware IP design is set in advance, future IoT applications will be able to improve security strength without time difficulties.

• 한국정보통신학회논문지
• /
• 제24권8호
• /
• pp.1037-1043
• /
• 2020

본 논문에서는 IoT 기기를 위한 저가, 초소형, 저 전력의 반도체 공정 기반 물리적 복제 불가능 보안회로를 소개한다. 제안하는 보안회로는 SRAM 구조의 인버터 간 교차결합 경로에 스위칭 회로를 연결하여 챌린지 입력을 인가함으로써 다수개의 입출력 쌍을 갖도록 한다. 그 결과 제안된 구조는 기존 SRAM 기반 물리적 복제 불가능 보안회로의 빠른 동작 속도와 비트 당 소요면적이 작은 장점을 유지하면서도 다수개의 입출력 쌍을 갖는다. 제안된 스위칭 SRAM 기반의 물리적 복제 불가능 보안회로는 성능 검증을 위해 180nm CMOS 공정을 이용하여 총 면적 0.095㎟ 의 칩으로 제작하였다. 측정 결과 4096-bit의 CRP, 0의 Intra-HD, 0.4052의 Inter-HD의 우수한 성능을 보였다.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2002년도 ITC-CSCC -1
• /
• pp.313-316
• /
• 2002

This paper presents the design and implementation of a crypto processor, a special-purpose microprocessor optimized for the execution of cryptography algorithms. This crypto processor can be used fur various security applications such as storage devices, embedded systems, network routers, etc. The crypto processor consists of a 32-bit RISC processor block and a coprocessor block dedicated to the SEED and triple-DES (data encryption standard) symmetric key crypto (cryptography) algorithms. The crypto processor has been designed and fabricated as a single VLSI chip using 0.5 $\mu\textrm{m}$ CMOS technology. To test and demonstrate the capabilities of this chip, a custom board providing real-time data security for a data storage device has been developed. Testing results show that the crypto processor operates correctly at a working frequency of 30MHz and a bandwidth o1240Mbps.

• 대한전자공학회논문지TE
• /
• 제39권1호
• /
• pp.46-54
• /
• 2002

정보 통신의 급속한 발전과 확산으로 전세계가 통신망으로 개방화되고, 정보 자체가 국가 경제 발전을 좌우하는 중요한 변수로 작용하게 되었다. 정보 보안은 특성상 각 국가마다 독단적인 정보보호시스템을 개발하여 독립적으로 그 비밀성을 유지해야 할 필요가 있다 이에 국내 암호 알고리즘의 활용 확대를 위해 국내 표준인 SEED 암호 알고리즘을 적용하여 Xilinx사 XCV300PQ240 칩을 타겟(target)으로 최대 동작 주파수 47.895MHz이고, 등가게이트는 27,285인 음성 암호화 칩을 설계하였다.

• 정보보호학회논문지
• /
• 제13권4호
• /
• pp.85-98
• /
• 2003

현재 co-processor를 탑재한 IC 칩이 계속 출시되고 있어 IC 칩의 연산 능력이 나날이 발전하고 있다. 또한, 무선 단말기 시장에는 간편하고 다양한 서비스를 제공하기 위해 IC 칩(Integrated Circuit Chip)을 내장한 무선 단말기 제품이 많이 출시되고 있다. 하지만 현재 IC 칩에 탑재된 co-processor의 연산 능력은 아직 유선 통신 환경의 연산 능력에 미치지 못하고 있어 기존 유선 통신 환경의 키 분배 프로토콜을 무선 통신 환경에 그대로 활용하기 어렵다. 따라서 본 논문에서는 무선 단말기의 제한적인 연산 능력을 고려하여 암호 전용 연산을 하는 co-processor를 무선 단말기에 탑재함으로써 연산 능력을 보완하고, 기존의 이동 통신 환경에서의 키 분배 프로토콜에서 제공하지 않는 보안 요구 사항을 만족하며, 사용자와 서버 양측에 연산 부담을 줄일 수 있는 무선 단말기 환경에 적합한 키 분배 프로토콜을 제안한다.