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Switched SRAM-Based Physical Unclonable Function with Multiple Challenge to Response Pairs

스위칭 회로를 이용한 다수의 입출력 쌍을 갖는 SRAM 기반 물리적 복제 불가능 보안회로

  • Baek, Seungbum (School of Electrical Engineering, Chungbuk National University) ;
  • Hong, Jong-Phil (School of Electrical Engineering, Chungbuk National University)
  • Received : 2020.07.16
  • Accepted : 2020.07.22
  • Published : 2020.08.31

Abstract

This paper presents a new Physical Unclonable Function (PUF) security chip based on a low-cost, small-area, and low-power semiconductor process for IoT devices. The proposed security circuit has multiple challenge-to-response pairs (CRP) by adding the switching circuit to the cross-coupled path between two inverters of the SRAM structure and applying the challenge input. As a result, the proposed structure has multiple CRPs while maintaining the advantages of fast operating speed and small area per bit of the conventional SRAM based PUF security chip. In order to verify the performance, the proposed switched SRAM based PUF security chip with a core area of 0.095㎟ was implemented in a 180nm CMOS process. The measurement results of the implemented PUF show 4096-bit number of CRPs, intra-chip Hamming Distance (HD) of 0, and inter-chip HD of 0.4052.

본 논문에서는 IoT 기기를 위한 저가, 초소형, 저 전력의 반도체 공정 기반 물리적 복제 불가능 보안회로를 소개한다. 제안하는 보안회로는 SRAM 구조의 인버터 간 교차결합 경로에 스위칭 회로를 연결하여 챌린지 입력을 인가함으로써 다수개의 입출력 쌍을 갖도록 한다. 그 결과 제안된 구조는 기존 SRAM 기반 물리적 복제 불가능 보안회로의 빠른 동작 속도와 비트 당 소요면적이 작은 장점을 유지하면서도 다수개의 입출력 쌍을 갖는다. 제안된 스위칭 SRAM 기반의 물리적 복제 불가능 보안회로는 성능 검증을 위해 180nm CMOS 공정을 이용하여 총 면적 0.095㎟ 의 칩으로 제작하였다. 측정 결과 4096-bit의 CRP, 0의 Intra-HD, 0.4052의 Inter-HD의 우수한 성능을 보였다.

Keywords

References

  1. T. Idriss, H. Idriss, and M. Bayoumi, "A PUF-based paradigm for IoT security," in 2016 IEEE 3rd World Forum on Internet of Things (WF-IoT), Reston: VA, pp. 700-705, Dec. 2016.
  2. U. Chatterjee, V. Govindan, R. Sadhukhan, D. Mukhopadhyay, R. S. Chakraborty, D. Mahata, and M. M. Prabhu, "Building PUF Based Authentication and Key Exchange Protocol for IoT Without Explicit CRPs in Verifi er Database," IEEE Transactions on Dependable and Secure Computing, vol. 16, no. 3, pp. 424-437, Jun. 2019. https://doi.org/10.1109/TDSC.2018.2832201
  3. Y. Zheng, S. S. Dhabu and C. Chang, "Securing IoT Monitoring Device using PUF and Physical Layer Authentication," in 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, pp. 1-5, May 2018.
  4. J. Y. Lee and L. Kolasani, "Security Based Network for Health Care System," Asia-pacific Journal of Convergent Research Interchange, vol. 1, no. 1, pp. 1-6, Mar. 2015. https://doi.org/10.21742/apjcri.2015.03.01
  5. H.-J. Han and D.-W. Park, "Cybersecurity of The Defense Information System network connected IoT Sensors," Journal of the Korea Institute of Information and Communication Engineering, vol. 24, no. 6, pp. 802-808, Jun. 2020.
  6. R. Maes and I. Verbauwhede, "Physically Unclonable Functions: A Study on the State of the Art and Future Research Directions," in Towards Hardware-Intrinsic Security, Berlin: Springer, pp. 3-37, Oct. 2010.
  7. Y. Gao, S. F. Al-Sarawi, and D. Abbott, "Physical unclonable functions," Nature Electronics, vol. 3, no. 2, pp. 81-91, Feb. 2020. https://doi.org/10.1038/s41928-020-0372-5
  8. J. Guajardo, S. S. Kumar, G.-J. Schrijen, and P. Tuyls, "FPGA Intrinsic PUFs and Their Use for IP Protection," in International Workshop on Cryptographic Hardware and Embedded Systems (CHES), Berlin: Springer, pp. 63-80, 2007.
  9. K.-U. Choi, S. Baek, J. Heo, and J.-P. Hong, "A 100% Stable Sense- Amplifier-Based Physically Unclonable Function With Individually Embedded Non-Volatile Memory," IEEE Access, vol. 8, pp. 21857-21865, Feb. 2020. https://doi.org/10.1109/access.2019.2961967
  10. K. Yang, Q. Dong, D. Blaauw, and D. Sylvester, "14.2 A physically unclonable function with BER <10-8 for robust chip authentication using oscillator collapse in 40nm CMOS," in 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, San Francisco: CA, pp. 1-3, Feb. 2015.
  11. X. Xi, H. Zhuang, N. Sun, and M. Orshansky, "Strong subthreshold current array PUF with 2 65 challenge-response pairs resilient to machine learning attacks in 130nm CMOS," in 2017 Symposium on VLSI Circuits, Kyoto, pp. C268-C269, Jun. 2017.
  12. S. Jeloka, K. Yang, M. Orshansky, D. Sylvester, and D. Blaauw, "A sequence dependent challenge-response PUF using 28nm SRAM 6T bit cell," in 2017 Symposium on VLSI Circuits, Kyoto, pp. C270-C271, Jun. 2017.