• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1571-1574
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• 2002

This paper describes a circuit and its operations of a programmable digital on-chip terminator designed with CMOS circuits which are used in high speed I/O interface. The on-chip terminator matches external reference resistor with the accuracy of ${\pm}$ 4.1％ over process, voltage and temperature variation. The digital impedance codes are generated in programmable impedance controller (PIC), and the codes are sent to terminator transistor arrays at input pads serially to reduce the number of signal lines. The transistor array is thermometer-coded to reduce impedance glitches during code update and it is segmented to two different blocks of thermometer-coded transistor arrays to reduce the number of transistors. The terminator impedance is periodically updated during hold time to minimize inter-symbol interferences.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1378-1381
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• 2002

This paper describes a control network which has a new node structure in the LonWorks networks. The proposed node structure is applicable to flexible and more complex applications which are impossible in the conventional Lonworks node structure. We implemented a node in order to evaluate the proposed control networks and verified the commercial feasibility and compatibility by experimenting the implemented node in the conventional Lonworks control networks.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.619-620
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• 2006

This paper presents a design of a 6-bit 2.704Gsamples/s D/A converter (DAC) for DS-CDMA UWB transceivers. The proposed DAC was designed with a current steering segmented 4+2 architecture for high frequency sampling rate. For low glitches, optimized deglitch circuit is adopted for the selection of current sources. The measured integral nonlinearity (INL) is -0.081 LSB and the measured differential nonlinearity (DNL) is -0.065 LSB. The DAC implemented in a 0.13um CMOS technology shows s spurious free dynamic range (SFDR) of 50dB from dc to Nyquist frequency. The prototype DAC consumes 28mW for a Nyquist sinusoidal output signal at a 2.704Gsamples/s. The chip has an active area of $0.76mm^2$.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.165-168
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• 2002

As the demand for higher data-rate chip-to-chip communication such as memory-to-controller, processor-to-processor increases, low cost high-speed serial links\ulcorner become more attractive. This paper describes a 0.25-fm CMOS 1.6Gbps/pin 4-level transceiver using Stub Series Terminated Logic for high Bandwidth. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by channel low pass effects, process-limited on-chip clock frequency, and serial link distance. The proposed transceiver uses multi-level signaling (4-level Pulse Amplitude Modulation) using push-pull type, double data rate and flash sampling. To reduce Process-Voltage-Temperature Variation and ISI including data dependency skew, the proposed high-speed calibration circuits with voltage swing controller, data linearity controller and slew rate controller maintains desirable output waveform and makes less sensitive output. In order to detect successfully the transmitted 1.6Gbps/pin 4-level data, the receiver is designed as simultaneous type with a kick - back noise-isolated reference voltage line structure and a 3-stage Gate-Isolated sense amplifier. The transceiver, which was fabricated using a 0.25 fm CMOS process, performs data rate of 1.6 ~ 2.0 Gbps/pin with a 400MHB internal clock, Stub Series Terminated Logic ever in 2.25 ~ 2.75V supply voltage. and occupied 500 * 6001m of area.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.791-794
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• 2003

The increasing computational capability of processors is driving the need for high bandwidth links to communicate and store the information that is processed. Such links are often an important part of multi processor interconnection, processor-to-memory interfaces and Serial-network interfaces. This paper describes a 0.11-${\mu}{\textrm}{m}$ CMOS 4 Gbp s/pin 3-Level transceiver using RSL/(Rambus Signaling Logic) for high bandwidth. This system which uses a high-gain windowed integrating receiver with wide common-mode range which was designed in order to improve SNR when operating with the smaller input overdrive of 3-Level. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by low pass effects of channel, process-limited on-chip clock frequency, and serial link distance. In order to detect the transmited 4Gbps/pin with 3-Level data sucessfully ,the receiver is designed using 3-stage sense amplifier. The proposed transceiver employes multi-level signaling (3-Level Pulse Amplitude Modulation) using clock multi phase, double data rate and Prbs patten generator. The transceiver shows data rate of 3.2 ~ 4.0 Gbps/pin with a 1GHz internal clock.

• Journal of Distribution Science
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• v.20 no.12
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• pp.23-33
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• 2022

Purpose: The objective of the study is to examine the role of approval goals, subjective norm, internal motivation, external motivation, attitude towards behavior, and perceived behavioral control on retail consumer's intention to consume fortified food in Pakistan. Research design, data, and methodology: The study was quantitative in nature. That is why the data were collected from 384 respondents approaching retail stores of Lahore, Gujranwala, and Faisalabad using mall intercept survey. Partial least squares structural equation modeling (PLS-SEM) was used to analyze the data. Results: The results show that approval goals significantly influence subjective norms. Secondly, subjective norms positively influence internal and external motivation. Thirdly, attitude towards behavior and internal motivation significantly impacted on intention. However, the findings of the study show, non-significant relationship of external motivation and perceived behavioral control with intention to consume fortified food. Conclusion: Theory of reasoned goal pursuit was used to investigate consumer intention to consume fortified food in Pakistan. This study is helpful for the marketers to create a word-of-mouth strategy to enhance positive word of mouth for the company, which ultimately beneficial to develop the distribution strategy of the firm. Fortified food is full of health enriched ingredients which is beneficial for society at large.

• The Korean Journal of Mycology
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• v.21 no.4
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• pp.310-315
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• 1993

Phanerochaete chrysosporium is a white rot fungus which secrets a family of lignin-degrading enzymes under nutrient limitation. Ligninase was extracellularly produced in agitated submerged cultures of P. chrysosporium, SC 26. Addition of veratryl alcohol(4 mM), and benzyl alcohol(10 mM) with 0.1% Tween 20 to the culture medium stimulated ligninase production. However, ligninase was not detected when both treatments of veratryl alcohol and benzyl alcohol without Tween 20 were added to the medium. Addition of 0.1 % Tween 20 to the culture medium had little effect on ligninase activity. The ligninase activity was maximum on day 5-8 for veratryl alcohol, and benzyl alcohol with 0.1 % Tween 20 additive medium.

• The Journal of the Korea Contents Association
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• v.17 no.2
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• pp.137-148
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• 2017

The purpose of this study is to develop a children's ego-resilience measurement scale and to examine the reliability and validity of the developed scale. Subjects consisted of 289 children of age 3 to 5 attending kindergarten and daycare centers located in Gwangju city and Chonnam province. Factor analysis, correlation analysis and reliability analysis were conducted using SPSS 18.0 and Amos 18.0 programs. The children's ego resilience scale consists of 26 items of 5 factors(attention concentration, emotion control, self efficacy, empathy, peer relationship) after the exploratory factor analysis. The confirmatory factor analysis revealed that RMSEA is .059, NNFI is .901 and CFI is .913. Pearson's product moment correlation coefficient were acceptable with this study's scale and KPRC. Chronbach ${\alpha}$ were also acceptable. Thus, the developed children's ego resilience measurement scale is reliable and valid.

• The Journal of the Korea Contents Association
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• v.16 no.5
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• pp.746-759
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• 2016

The purpose of this study was examine the effects of STEAM(Science-Technology-Engineering-Art-mathematics) activities on young children's scientific process skill ability and problem solving ability. Subjects were 34 five-year-old young children from S and H child care centers located in G city. Subjects were divided into an experimental(n=17) and a control group(n=17). The experimental group took part in the STEAM activities during 8 weeks, while the control group took part in the traditional science activities. The procedure for this study consisted of a pre-study, a pre-test, the treatment, and a post-test schedule. The results of this study were as follows: First, the experimental group showed significantly higher score than the control group in total scientific process skill ability. Second, the experimental group showed significantly higher score than the control group in total problem solving ability. These findings suggest that the experience of STEAM activities for young children can be effective teaching-learning methods for young children's scientific process skill ability and problem solving ability.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.1A
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• pp.104-112
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• 2005

Some design techniques for high speed and low power pipelined 8-bit ADC are described. To perform high-speed operation with relatively low power consumption, open loop architecture is adopted, while closed loop architecture (with MDAC) is used in conventional pipeline ADC. A distributed track and hold amplifier and a cascading structure are also adopted to increase the sampling rate. To reduce the power consumption and the die area, the number of amplifiers in each stage are optimized and reduced with proposed zero-crossing point generation method. At 500-MHz sampling rate, simulation results show that the power consumption is 210mW including digital logic with 1.8V power supply. And the targeted ADC achieves ENOB of about 8-bit with input frequency up to 200-MHz and input range of 1.2Vpp (Differential). The ADC is designed using a $0.18{\mu}m$ 6-Metal 1-Poly CMOS process and occupies an area of $900{\mu}m{\times}500{\mu}m$