• 대한전자공학회논문지SD
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• 제40권4호
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• pp.13-20
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• 2003

반도체 소자이론에 근거한 집적회로용 BJT의 역포화 전류 모델을 제시한다. 공정 조건으로부터 베이스 영역의 불순물 분포를 구하는 방법과 원형 에미터 구조를 갖는 Lateral PNP BJT와 Vertical NPN BJT의 베이스 Gummel Number를 정교하게 계산하는 방법을 제시한다. 제안된 방법의 타당성을 검증하기 위해 20V와 30V 공정을 기반으로 제작한 NPN BJT와 PNP BJT의 역포화 전류를 실측치와 비교한 결과, NPN BJT는 6.7%의 평균상대오차를 보이고 있으며 PNP BJT는 6.0%의 평균 상태오차를 보인다.

• 전자공학회논문지A
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• 제33A권11호
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• pp.1-9
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• 1996

In the following paper, new architectural algorithm of clock and data recovery circuit is proposed for 622.08 Mbps optical communication receiver. New algorithm makes use of charge pump PLL using voltage controlled ring oscillator and extracts 8-channel 77.76 MHz clock signals, which are delayed by i/8 (i=1,2, ...8), to convert and recover 8-channel parallel data from 662.08 Mbps MRZ serial data. This circuit includes clock genration block to produce clock signals continuously even if input data doesn't exist. And synchronization of data and clock is doen by the method which compares 1/2 bit delayed onput data and decided dta by extracted clock signals. Thus, we can stabilize frequency and phase of clock signal even if input data is distorted or doesn't exist and simplify receiver architecture compared to traditional receiver's. Also it is possible ot realize clock extraction, data decision and conversion simulataneously. Verification of this algorithm is executed by DESIGN CENTER (version 6.1) using test models which are modelized by analog behavior modeling and digital circuit model, modified to process input frequency sufficiently, in SPICE.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권2호
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• pp.208-222
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• 2015

For the performance-efficient integration of IPs on an SoC utilizing heterochronous multi-clock domains, we propose a synchronization scheme that causes low latency overhead when data are crossing clock boundaries. The proposed synchronization scheme is composed of a clock predictor and a synchronizer. The clock predictor of a sender clock domain produces a predicted clock that is used in a receiver clock domain to detect possible synchronization failures in advance. When the possible synchronization failures are detected, a synchronizer at the receiver delays data-capture times to avoid the possible synchronization failures. From the simulation of the proposed scheme through SPICE modeling using a Chartered $0.18{\mu}m$ CMOS process, we verified the functionalities and timing behavior of the clock predictor and the synchronizer. The simulation results show that the clock predictor produces a predicted clock before a synchronization failure, and the synchronizer samples data correctly using the predicted clock.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권4호
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• pp.463-470
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• 2014

A Verilog model is proposed for transmission lines to perform the all-Verilog simulation of high-speed chip-to-chip interface system, which reduces the simulation time by around 770 times compared to the mixed-mode simulation. The single-pulse response of transmission line in SPICE model is converted into that in Verilog model by converting the full-scale analog signal into an 11-bit digital code after uniform time sampling. The receiver waveform of transmission line is calculated by adding or subtracting the single-pulse response in Verilog model depending on the transmitting digital code values with appropriate time delay. The application of this work to a USB 2.0 high-speed PHY interface reduces the simulation time to less than three minutes with error less than 5% while the mixed-mode simulation takes more than two days for the same circuit.

• Smart Structures and Systems
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• 제14권2호
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• pp.247-266
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• 2014

Conventional cantilevered piezoelectric energy harvesters (PEHs) are usually fabricated with continuous electrode configuration (CEC), which suffers from the electrical cancellation at higher vibration modes. Though previous research pointed out that the segmented electrode configuration (SEC) can address this issue, a comprehensive evaluation of the PEH with SEC has yet been reported. With the consideration of delivering power to a common load, the AC outputs from all segmented electrode pairs should be rectified to DC outputs separately. In such case, theoretical formulation for power estimation becomes challenging. This paper proposes a method based on equivalent circuit model (ECM) and circuit simulation to evaluate the performance of the PEH with SEC. First, the parameters of the multi-mode ECM are identified from theoretical analysis. The ECM is then established in SPICE software and validated by the theoretical model and finite element method (FEM) with resistive loads. Subsequently, the optimal performances with SEC and CEC are compared considering the practical DC interface circuit. A comprehensive evaluation of the advantageous performance with SEC is provided for the first time. The results demonstrate the feasibility of using SEC as a simple and effective means to improve the performance of a cantilevered PEH at a higher mode.

• 전자공학회논문지C
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• 제36C권5호
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• pp.13-26
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• 1999

본 논문은 다양한 회로 연결선 모형 중에서 연결선 변수 및 동작 환경에 다라 최적 모형을 쉽게 선택할 수 있는 기준을 제시하고자 한다. 이를 위하여 먼저 연결선의 총 저항, 인덕턴스, 커패시턴스 값 및 신호의 동작주파수를 기반으로 정량적 모형화 오차 분석에 근거하여 인덕턴스의 영향을 고려하여 모형화해야 하는 RLC-class 모형 영역과 그럴 필요가 없는 RC-class모형 영역으로 분할하는 방법을 제시한다. 칩 내부 연결선의 대부분을 차지하는 RC-class 회로 모형은 모형 차수 축소 기법을 통하여 효율적으로 해석될 수 있다. RLC-class 회로 모형은 주어진 허용 모형화 오차 및 전기 변수에 따라 ILC(Iterative Ladder Circuit) 거시 모형, MC(Method of Characteristics)거시 모형 및 상태 기반 컨벌루션(comvolution) 방법 중에서 최적인 모형을 선정하게 된다. 본 논문은 SPICE류의 범용 회로 시뮬레이션 앨고리즘을 가정할 때, 세부 모형들의 시뮬레이션 비용을 감안하고서 최적 모형을 찾는 영역 구성도를 제시한다. 본 논문에서 제시하는 거시모형화 방법은 회로의 수동성을 유지하며, 따라서 무조건적 안정도를 보장할 수 있다.

• 대한의용생체공학회:의공학회지
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• 제16권4호
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• pp.415-424
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• 1995

Combined models, specified by two or more modeling formalisms, can represent a wide variety of complex systems. This paper describes a methodology for the development of combined models in two model types of discrete event and continuous process. The methodology is based on transformation of continuous state space into discrete one to homomorphically represent dynamics of continuous processes in discrete events. This paper proposes a formal structure which can combine model of the DES and the CS within a framework. The structure employs the DEVS formalism for the DES models and differential or polynomial equations for the CS models. To employ the proposed structure to specify a DEVS/CS combined model, a modeler needs to take the following steps. First, a modeler should identify events in the CS and transform the states of the CS into the DES. Second, a modular employs the formalism to specify the system as the DES. Finally, a moduler developes sub-models for the CS and continguos states of the DES and establishs one-to-one correspondence between the sub-models and such states. The proposed formal structre has been applied to develop a DEVS/CS combined model for the human cardiovascular system. For this, the cardiac cycle is partitioned into a set of phases based on events identified through observation. For each phase, a CS model has been developed and associated with the phase. To validate the DEVS/CS combined model developed, then simulate the model in the DEVSIM + + environment, which is a model simulation results with the results obtained from the CS model simulation using SPICE. The comparison shows that the DEVS/CS combined model adequately represents dynamics of the human heart system at each phase of cardiac cycle.

• 대한전자공학회논문지SD
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• 제38권2호
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• pp.114-121
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• 2001

능동제어형 전계방출 디스플레이의 전자공급원으로서 능동제어형 전계 에미터 어레이의 회로모델이 제안되었다. 능동제어형 전계 에미터 어레이는 전계방출을 안정화시키고 저전력구동을 위한 수소화 된 비정질 실리콘 박막 트랜지스터와 Spindt형 Mo 전계 에미터 어레이로 구성되었고 같은 유리기판 위에 제작되었다. 비정질 박막 트랜지스터와 Spindt형 Mo 전계 에미터 어레이의 전기적 특성으로부터 추출된 기본 모델 변수는 제안된 능동제어형 전계 에미터 어레이 회로모델에 입력되었고 SPICE 회로 시뮬레이터를 사용하여 특성을 분석하였다. 제작된 소자의 측정값과 DC 시뮬레이션 결과를 비교한 결과 두 값이 상당히 일치함으로써 등가회로 모델의 정확성을 확인하였다. 또한 제작된 소자의 transient 시뮬레이션 결과 전계 에미터 어레이의 게이트 커패시턴스와 TFT의 구동능력이 반응시간에 가장 크게 영향을 끼치고 있음을 확인하였다. 제작된 능동제어형 전계방출 에미터 어레이는 pulse width modulation으로 구동하는 경우 15㎲의 반응시간을 얻었고 이 값으로는 4bit/color의 계조(gray scale)표현이 가능하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권2호
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• pp.174-179
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• 2017

We designed the CMOS analog integrate and fire (I&F) neuron circuit for driving memristor based on resistive-switching random access memory (RRAM). And we fabricated the RRAM device that have $HfO_2$ switching layer using atomic layer deposition (ALD). The RRAM device has gradual set and reset characteristics. By spice modeling of the synaptic device, we performed circuit simulation of synaptic device and CMOS neuron circuit. The neuron circuit consists of a current mirror for spatial integration, a capacitor for temporal integration, two inverters for pulse generation, a refractory part, and finally a feedback part for learning of the RRAM. We emulated the spike-timing-dependent-plasticity (STDP) characteristic that is performed automatically by pre-synaptic pulse and feedback signal of the neuron circuit. By STDP characteristics, the synaptic weight, conductance of the RRAM, is changed without additional control circuit.

• 전자공학회논문지
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• 제54권4호
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• pp.25-31
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• 2017

본 논문에서는 270/540/750/1500-Mb/s 동작속도를 갖는 영상신호 전송용 시리얼 송신기 칩을 $0.13-{\mu}m$ CMOS 공정을 이용하여 구현하였다. 전송 채널은 저가형 RG-58 계열의 5C-HFBT-RG6T 동축 케이블로서, 싱글 BNC 커넥터로 연결되어 있으며, 1.5-GHz 주파수에서 케이블 손실은 최대 45 dB이다. 이를 RLGC 모델링을 통해 SPICE용 회로로 구현하였고, 케이블 손실측정결과와 매우 유사한 특성을 갖는다. 신호감쇄의 보상은 송신기 회로의 프리앰퍼시스 기능 및 수신단의 이퀄라이저 기능을 통해 복원하며, 송신기 칩의 측정 결과 270-Mb/s, 540-Mb/s, 750-Mb/s 및 1.5-Gb/s 동작속도를 모두 만족하며, 프리앰퍼시스 기능을 OFF 했을 때에도 1.5 Gb/s에서 $370-mV_{pp}$ 출력전압을 갖는다. 칩의 전력소모는 1.2/3.3-V 전원전압으로부터 104 mW, 칩 면적은 I/O 패드를 포함하여 $1.65{\times}0.9mm^2$ 이다.