• 한국지능시스템학회논문지
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• 제24권5호
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• pp.457-461
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• 2014

생물학적 신경 세포의 모델링을 위한 펄스타입 실리콘 뉴런 회로를 $0.18{\mu}m$ CMOS 공정을 이용하여 반도체 집적회로로 설계하였다. 제안하는 뉴런 회로는 입력 전류신호를 위한 커패시터 입력단과, 출력 전압신호 생성을 위한 증폭단 및 펄스신호 초기화를 위한 MOS 스위치로 구성된다. 전압신호 입력을 전류신호 출력으로 변환하는 기능의 시냅스 회로는 몇 개의 PMOS와 NMOS 트랜지스터로 이루어지는 범프회로를 사용한다. 제안하는 뉴런 모델의 검증을 위하여, 2개의 뉴런과 시냅스가 직렬연결된 뉴런체인을 구성하여 SPICE 모의실험을 실시하였다. 모의실험 결과, 뉴런신호의 생성과 시냅스 전달특성의 정상적인 동작을 확인하였다.

• 정보처리학회논문지C
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• 제12C권7호
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• pp.989-998
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• 2005

최근 대부분의 정보시스템은 대규모 및 광역화되고 있으며 이에 따른 사이버 침해사고와 해킹의 위험성이 증대되고 있다. 이를 해결하기 위하여 정보보호 기술중에서 보안위험분석 분야의 연구가 활발하게 이루어지고 있다. 하지만 다양한 자산과 복잡한 네트워크의 구조로 인하여 위험도를 현실에 맞게 산정한다는 것이 사실상 불가능하다. 특히, 취약성과 위협의 증가는 시간에 따라 계속 증가하며 이에 대응하는 보호대책은 일정 시간이 흐른 뒤 이루어지므로 제시된 결과가 효과적인 위험분석의 결과로 볼 수 없다. 따라서. 정보시스템에 대한 모델링 기법을 통하여 정보시스템의 구조를 단순화하고 사이버 침해의 방향성을 도식화함으로써 위험분석 및 피해 파급 영향 분석을 보호대책 수립의 허용 시간 내에서 이루어질 수 있도록 해야 한다 이에 따라, 본 논문에서는 보안 위험을 분석할 수 있도록 SPICE와 Petri-Net을 이용한 정보시스템의 모델링 기법을 제안하고, 이 모델링을 기반으로 사례연구를 통하여 위험분석 시뮬레이션을 수행하고자 한다.

• Journal of Electrical Engineering and Technology
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• 제10권3호
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• pp.1138-1143
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• 2015

Effects of fabrication process variations on impedance of microelectrodes integrated on a neural probe were examined through equivalent circuit modeling and SPICE simulation. Process variation and the corresponding range were estimated based on experimental data. The modeling results illustrate that the process variation induced by metal etching process was the dominant factor in impedance variation. We also demonstrate that the effect of process variation is frequency dependent. Another process variation that was examined in this work was the thickness variation induced by deposition process. The modeling results indicate that the effect of thickness variation on impedance is negligible. This work provides a means to predict the variations in impedance values of microelectrodes on neural probe due to different process variations.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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• pp.447-450
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• 2004

The modeling circuit becomes more important in developing various magnetic devices regarding the fact that the competitive architecture and circuitry should be developed simultaneously. In this paper, we introduce a modeling circuit for hysteresis characteristic of a magnetic device, which is a major characteristic in the spin dependent magnetic material. This transistor-level model is conspicuous in that it can be usefully embodied in real circuits rather than conventional SPICE models are only for simulations.

• 전자공학회논문지A
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• 제33A권6호
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• pp.206-219
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• 1996

This paper describes a data structure and evaluation algorithm to improve the perofmrances MOS logic-with-timing simulation in computation and accuracy. In order to efficiently simulate the logic and timing of driver-load networks, (1) a tree data structure to represent the mutual interconnection topology of switches and nodes in the driver-lod network, and (2) an algebraic modeling to efficiently deal with the new represetnation, (3) an evaluation algorithm to compute the linear resistive and capacitive behavior with the new modeling of driver-load networks are developed. The higher modeling presented here supports the structural and functional compatibility with the linear switch-level to simulate the logic-with-timing of digital MOS circuits at a mixed-level. This research attempts to integrate the new approach into the existing simulator RSIM, which yield a mixed-klevel logic-with-timing simulator MIXIM. The experimental results show that (1) MIXIM is a far superior to RSIM in computation speed and timing accuracy; and notably (2) th etiming simulation for driver-load netowrks produces the accuracy ranged within 17% with respect ot the analog simulator SPICE.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집 Vol.14 No.1
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• pp.201-204
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• 2001

In this paper, for modeling of electrical characteristics in Poly Silicon Thin Film Transistors with process parameters set up optimum values, So, the I-V characteristics of poly silicon TFT parameters are examined and simulated in terms of the variations in process parameter. And these results compared and analyzed simulation values with examination value. The simulation program for characteristic analysis used SUPREM IV for processing, Matlab for modeling by mathematics, and SPICE for electric characteristic of devices. Input parameter for simulation characteristics is like condition of device process sequence, these electric characteristic of $I_D-V_D$ $I_D-V_G$, variations of grain size. The Gate oxide thickness of poly silicon are showed similar results between real device characteristics and simulation characteristics.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집
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• pp.201-204
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• 2001

In this paper, for modeling of electrical characteristics in Poly Silicon Thin Film Transistors with process parameters set up optimum values. So, the I-V characteristics of poly silicon TFT parameters are examined and simulated in terms of the variations in process parameter. And these results compared and analyzed simulation values with examination value. The simulation program for characteristic analysis used SUPREM IV for processing, Matlab for modeling by mathematics, and SPICE for electric characteristic of devices. Input parameter for simulation characteristics is like condition of device process sequence, these electric characteristic of I$_{D}$-V$_{D}$, I$_{D}$-V$_{G}$, variations of grain size. The Gate oxide thickness of poly silicon are showed similar results between real device characteristics and simulation characteristics.ristics.

• 반도체디스플레이기술학회지
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• 제16권3호
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• pp.59-64
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• 2017

As the demand on displays increases, new thin-film transistors such as metal oxide transistor are continuously being invented. When designing a circuit consisting of such new transistors, a new transistor model based on proper charge transport mechanisms is needed for each of them. In this paper, a modeling framework which enables to choose charge transport mechanisms that are limited to certain operation regions and assemble them into a transistor model instead of making an integrated transistor model dedicated to each transistor. The framework consists of a graphic user interface to choose charge transport models and a current calculation part, which is also implemented in AIM-SPICE for circuit simulation.

• 대한전기학회논문지
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• 제40권5호
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• pp.531-539
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• 1991

We develop an analytical model of the static and the dynamic characteristics of amorphous silicon thin film transistors (a-Si TFTs) in order to incorporate into a widely used circuit simulator such as SPICE. The critical parameters considered in our analytical model of a-Si TFT are the power factor (XN) of saturation source-drain current and the effective channel length (L') at saturation region. The power factor, XN must not always obey so-called

• 센서학회지
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• 제14권2호
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• pp.96-100
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• 2005

The planar Schottky diodes were fabricated and modeled to probe the device applicability of the cracked GaN epitaxial layer on a (111) silicon substrate. On the unintentionally n-doped GaN grown on silicon, we deposited Ti/Al/Ni/Au as the ohmic metal and Pt as the Schottky metal. The ohmic contact achieved a minimum contact resistivity of $5.51{\times}10.5{\Omega}{\cdot}cm^{2}$ after annealing in an $N_{2}$ ambient at $700^{\circ}C$ for 30 sec. The fabricated Schottky diode exhibited the barrier height of 0.7 eV and the ideality factor was 2.4, which are significantly lower than those parameters of crack free one. But in photoresponse measurement, the diode showed the peak responsivity of 0.097 A/W at 300 nm, the cutoff at 360 nm, and UV/visible rejection ratio of about $10^{2}$. The SPICE(Simulation Program with Integrated Circuit Emphasis) simulation with a proposed model, which was composed with one Pt/GaN diode and three parasitic diodes, showed good agreement with the experiment.