• The Journal of Society for e-Business Studies
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• v.18 no.4
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• pp.83-105
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• 2013

There are two ways to assess data quality : measurement of data itself and assessment of data quality management process. Recently maturity assessment of data quality management process is used to ensure and certify the data quality level of an organization. Following this trend, the paper presents the process reference model which is needed to assess data quality management process maturity. First, the overview of assessment model for data quality management process maturity is presented. Second, the process reference model that can be used to assess process maturity is proposed. The structure of process reference model and its detail processes are developed based on the process derivation approach, basic principles of data quality management and the basic concept of process reference model in SPICE. Furthermore, characteristics of the proposed model are described compared with ISO 8000-150 processes.

• Journal of KIISE:Software and Applications
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• v.26 no.3
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• pp.412-421
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• 1999

소프트웨어 개발 및 시스템을 구현하기 위해 사용되고 있는 대표적인 프로세스 모델이 IEEESTD1074-1991, ISO/IEC DIS12207-1, SPICE 모델, MIL-STD 498이다. 이들을 실제 국내 프로젝트들에 적용하기 위해 여러 가지 해결방안이 연구되고 있다. 일반적으로 프로젝트을 수행할 때, 개발 이전 단계 프로세스 설계의 실패는 전체 프로젝트 공정에 영향을 준다. 본 논문에서는 프로세스 중심 소프트웨어 엔지니어링 환경을 기반으로 하여 개발 이전 단계의 프로세스를 설계하는 방법을 제안한다. 이 방법은 프로세스, 활동, 테스크들의 연관관계를 도식화하고 있다. 그리고 설계된 결과를 국내 프로젝트들에 적용, 그 결과를 분석한다.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.2
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• pp.146-156
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• 2002

In this paper, a new virtual-straight line parameter determination methodology and fast time domain simulation technique for non-uniform interconnects are presented and verified. Time domain signal response of interconnects circuit considering the characteristic of non-linear transistor is performed by using model order reduction method. Since model order reduction method is peformed by using per unit length parameters, virtual- straight line parameters for non-uniform interconnects are determined. Its method is integrated into Berkeley SPICE and shown that time domain signal responses using proposed method have a good agreement with the results of conventional circuit simulator HSPICE. The proposed method can be efficiently employed in the high-performance VLSI circuit design since it can provide a fast and accurate time domain signal response of complicated multi - layer interconnects.

• Journal of IKEEE
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• v.3 no.2 s.5
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• pp.226-235
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• 1999

To investigate SPICE noise model and the behavior of its parameters, 1/f noise of NMOS devices fabricated by BiCMOS process is measured and compared to the various noise models and measured results. For the long channel devices, bias dependence of the drain current noise power spectral density $S_{Id}$ of NMOS is similar to the previous results. Equivalent gate noise power spectral density $S_{Vg}$ shows weak dependence on the gate and drain voltages in long channel NMOS as the previous results. However, it is shown that most of published noise models are difficult to apply to short channel devices. Therefore, in this study, with comparison of our experimental results, we have tried to find the model of 1/f noise, appropriate for our NMOS device fabricated by BiCMOS process.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.8-16
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• 1999

This paper presents a new simulation-based analog cell synthesis approach with improved simulation efficiency For the hierarchical synthesis of analog cells we developed the sub-circuit optimizers such as current mirror and differential input stage. Each sub-circuit optimizer can be used for synthesis of analog cells such as OTA(operational transconductance amplifier), 2-stage OP-AMP and comparator. To reduce the time spending of the simulation-based synthesis we propose 2-stage searching scheme and simulation data reusing scheme. With those schemes the synthesis time spending of OTA was reduced from 301.05sec to 56.52sec by 81.12%. Since our synthesis system doesn't need other additional physical parameters except SPICE parameters, and is independent of the process and its model level, the time spending to port to other process is minimized. We synthesized OTA and 2-stage OP-AMP respectively with our approach to show its usefulness.

• 전자공학회논문지 IE
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• v.46 no.1
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• pp.16-22
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• 2009

Integrated circuit of a pulse-type neuron for Hodgkin-Huxley model is implemented in a $0.5{\mu}m$ 1 poly 2 metal CMOS technology. Proposed pulse-type neuron model consist of input stage with summing function and pulse generating block which make neuron pulse above threshold value. Pulse generating circuit consist of several transistors, capacitors and negative resistor with a charge supply function. SPICE simulation results show that neuron pulse is generated above threshold current of 70 nA. Measurements of the fabricated pulse type neuron chip in condition of 5 V power supply are shown and compared with the simulated results.

• Proceedings of the Korea Multimedia Society Conference
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• 2003.05b
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• pp.733-736
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• 2003

최근 소프트웨어 프로세스 개선을 통하여 개발되는 소프트웨어의 품질을 향상시키기 위하여 개발 조직의 ?f발 능력과 생산성을 향상시키기 위하여 많은 회사들이 관심을 보이고 있다. 본 논문에서는 다양한 프로세스 심사 모델의 장점을 흡수하면서 조직 유형 및 프로젝트 규모에 제약 없이 프로세스 심사를 위한 개념을 제공하는 ISO/IEC 15504(SPICE)를 설명하고 최근의 심사사례를 바탕으로 전반적인 심사과정을 소개한다.

• Journal of the Korean Institute of Intelligent Systems
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• v.24 no.5
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• pp.457-461
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• 2014

Using $0.18{\mu}m$ CMOS process silicon neuron circuit of the pulse type for modeling biological neurons, were designed in the semiconductor integrated circuit. Neuron circuiSt providing is formed by MOS switch for initializing the input terminal of the capacitor to the input current signal, a pulse signal and an amplifier stage for generating an output voltage signal. Synapse circuit that can convert the current signal output of the input voltage signal, using a bump circuit consisting of NMOS transistors and PMOS few. Configure a chain of neurons for verification of the neuron model that provides synaptic neurons and two are connected in series, were performed SPICE simulation. Result of simulation, it was confirmed the normal operation of the synaptic transmission characteristics of the signal generation of nerve cells.

• Proceedings of the Korean Information Science Society Conference
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• 2003.04c
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• pp.40-42
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• 2003

최근 국내 기업들은 소프트웨어 프로세스 심사를 통하여 기업의 프로세스 성숙도 향상과 개발되는 제품의 품질을 향상시키고자 하는 관점에서 CMM과 SPICE와 같은 프로세스 모텔을 적용하고 있다. 이 모델들은 소프트웨어 프로세스가 일정 수준의 성숙도를 지나면 측정을 활용하여 성숙도를 높일 수 있도록 모델을 제시하고 있으며, 이는 소프트웨어 개발의 지표들을 정량적인 수치로 객관화하여 관리하도록 권고하고 있다. 본 논문에서는 Embedded 소프트웨어를 개발하는 기업에서 측정을 통하여 지표들을 정량적으로 관리하고 각 지표들 간의 상관 관계를 분석하여 메트릭스와 시장 점유율간의 의존도 분석 사례를 제시한다.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.65-72
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• 2013

This paper presents design methodology for Memristor-CMOS circuits and its application to primitive IPs design. We proposed a Memristor model and designed basic elements, Memristor AND/OR gates. The primitive IPs based on a Memristor-CMOS technology is proposed for a Memristive system design. The netlists of IPs are extracted from the layouts of Memristor-CMOS and is verified with SPICE-like Memristor model under $0.18{\mu}m$ CMOS technology. As a result, an example design Memristor-CMOS full adder has only 47.6 % of silicon area compare to the CMOS full-adder.