• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.6
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• pp.491-495
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• 2007

This paper has demonstrated the electrical properties of SiGe pMOSFETs fabricated on both bulk-Si and PD SOI substrates. Two principal merits, the mobility increase in strained-SiGe channel and the parasitic capacitance reduction of SOI isolation, resulted in improvements in device performance. It was observed that the SiGe PD SOI could alleviate the floating body effect, and consequently DIBL was as low as 10 mV/V. The cut-off frequency of device fabricated on PD SOI substrate was roughly doubled in comparison with SiGe bulk: from 6.7 GHz to 11.3 GHz. These experimental result suggests that the SiGe PD SOI pMOSFET is a promising option to drive CMOS to enhance performance with its increased operation frequency for high speed and low noise applications.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.8
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• pp.706-710
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• 2008

The substrate bias effect on the current level of SOI-MOSFETs for high temperature operation has been investigated. In this work, we demonstrate the current level of SOI-MOSFETs can be controlled at different temperatures by applying a control bias to the substrate, showing that all current levels below T=150$^{\circ}C$ can be adjusted to a constant current level. 2D numerical simulation results show that substrate bias effectively controls the current conduction; as the substrate bias effectively lower the potential of the channel, inversion carrier generation is effectively controlled and consequently a constant current conduction level is achieved up to T=150$^{\circ}C$. We also demonstrate that the device simulated in this work has same operation at any temperature below T=150$^{\circ}C$ through mixed mode simulation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.485-488
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• 1999

In this paper, the effects of back-gate bias on n-channel SOI MOSFETs has been systematically investigated. Back-gate surface is accumulated when negative bias is applied. It is found that the driving current ability of SOI MOSFETs is reduced because the threshold voltage and subthreshold slope are increased and transconductance is decreased due to the hole accumulation in Si body.

• Korean Journal of Materials Research
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• v.18 no.5
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• pp.272-276
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• 2008

In submicron MOSFET devices, maintaining the ratio between the channel length (L) and the channel depth (D) at 3 : 1 or larger is known to be critical in preventing deleterious short-channel effects. In this study, n-type SOI-MOSFETs with a channel length of $0.1\;{\mu}m$ and a Si film thickness (channel depth) of $0.033\;{\mu}m$ (L : D = 3 : 1) were virtually fabricated using a TSUPREM-4 process simulator. To form functioning transistors on the very thin Si film, a protective layer of $0.08\;{\mu}m$-thick surface oxide was deposited prior to the source/drain ion implantation so as to dampen the speed of the incoming As ions. The p-type boron doping concentration of the Si film, in which the device channel is formed, was used as the key variable in the process simulation. The finished devices were electrically tested with a Medici device simulator. The result showed that, for a given channel doping concentration of $1.9{\sim}2.5\;{\times}\;10^{18}\;cm^{-3}$, the threshold voltage was $0.5{\sim}0.7\;V$, and the subthreshold swing was $70{\sim}80\;mV/dec$. These value ranges are all fairly reasonable and should form a 'magic region' in which SOI-MOSFETs run optimally.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.10
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• pp.32-38
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• 2003

This works reports the measurement and analysis results on the hot electron induced device degradation in Gate-All-Around SOI MOSFET's, which were fabricated using commercially available SIMOX material. It is observed that the worst-case condition of the device degradation in nMOSFETs is $V_{GS}$ = $V_{TH}$ due to the higher impact ionization rate when the parasitic bipolar transistor action is activated. It is confirmed that the device degradation is caused by the interface state generation from the extracted degradation rate and the dynamic transconductance measurement. The drain current degradation with the stress gate voltages shows that the device degradation of pMOSFETs is dominantly governed by the trapping of hot electrons, which are generated in drain avalanche hot carrier phenomena.r phenomena.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.54-61
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• 2011

In this paper, a simple analytical model for deriving the I-V characteristics of a cylindrical surrounding gate SOI MOSFET with intrinsic silicon core is suggested. The Poisson equation in the intrinsic silicon core and the Laplace equation in the gate oxide layer are solved analytically. The surface potentials at both source and drain ends are obtained by means of the bisection method. From them, the surface potential distribution is used to describe the I-V characteristics in a closed-form. Simulation results seem to show the dependencies of the I-V characteristics on the various device parameters and applied bias voltages within a range of satisfactory accuracy.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.10
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• pp.1910-1915
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• 2007

An accurate and simple method to extract equivalent circuit parameters of fully-depleted silicon-on-insulator MOSFETs small-signal modeling operating at RF frequencies including the non-quasi static effects is presented in this article. The advantage of this method is that a unique and physically meaningful set of intrinsic equivalent circuit parameters is extracted by de-embedding procedure of extrinsic elements such as parasitic capacitances and resistances of MOSFETs from measured S-parameters using simple Z- and Y- matrices calculations. The calculated small-signal parameters using the presented extraction method give modeled Y-parameters which are in good agreement with the measured Y-parameters from 0.5 to 20GHz.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.8
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• pp.695-698
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• 2008

We investigated the characteristics of Strained-Si-on-Insulator (sSOI) MOSFETs with 0.7% tensile strain. The sSOI MOSFETs have superior subthreshold swing under 70 mV/dec and output current. Especially, the electron and hole were increased in sSOI MOSFET. The electron and hole mobility in sSOI MOSFET were 286$cm^2/Vs$ and 151$cm^2/Vs$, respectively. The carrier mobility enhancement is due to the subband splitting by 0.7% tensile strain.

• Proceedings of the KIEE Conference
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• 2002.11a
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• pp.159-160
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• 2002

본 논문에서는 반도체 응용부문 중 그 활용도가 높은 MOSFET(Metal-Oxide-Semiconductor Field Effect Transistor)의 새로운 구조를 제안하였다. 제안한 소자를 가지고 전자회로의 구성할 때 인접 디바이스들과 연계되어 발생되는 래치 업(latch-up)을 근본적으로 제거하고, 개별소자의 완전한 절연을 실현하였으며 누설전류 또한 제거된다. 이는 SOI기판 위에 벌크실리콘 공정을 이용하여 구현된다. 즉, 소자 양옆의 트랜치 웰(Trench-well)과 SOI 기판의 절연층으로 소자의 독립성을 지켜준다. 또한 게이트 절연층을 트랜치 구조로 기존 MOS구조의 채널 부분에 위치시키고 드레인과 소스를 위치시켜 자연적으로 자기정렬이 되어진다. 이와 같은 과정으로 게이트-소스, 게이트-드레인 기생 커패시터의 효과를 현저히 줄일 수 있다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.21-22
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• 2005

Partially-depleted Silicon on insulator metal-oxide-semiconductor field- effect transistors (PD-SOI MOSFETs) with Silicon-germanium (SiGe) layer is investigated. This structure uses SiGe layer to reduce the kink effect in the floating body region near the bottom channel/buried oxide interface. Among many design parameters influencing the performance of the device, Ge composition is presented most predominant effects, simulation results show that kink effect is reduced with increase the Ge composition. Because the bandgap of SiGe layer is reduced at higher Ge composition, the hole current between body and SiGe layer is enhanced.