• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 정기총회 및 추계학술대회 논문집 학회본부
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• pp.192-194
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• 1993

In this paper, a silicon piezoresistive accelerometer of which the cantilevers have uniform thickness is designed and fabricated with SOI wafer. The accelerometer consists of a seismic mass and four cantilevers, and is fabricated mainly by the anisotropic etching method using EPW etchant. The fabrication processes are that of the frontside processes including the etching of the cantilevers and the doubleside alignment holes, the diffusion of the piezoresisters and patterning of the contact windows, and the metal connection process, and that of the backside processes including the etching of the shallow cavity and the seismic mass. Because of the uniformity of thickness, the performance of the accelerometer fabricated with SOI wafer is expected to be better than that of accelerometer fabricated by the time-controlled etching method.

• 한국결정성장학회지
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• 제10권1호
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• pp.13-16
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• 2000

Progress in Si crystal and wafer technologies is discussed on single crystal growth, wafer fabrication, epitaxial growth, gettering, 300 mm and SOI. As for bulk crystal growth, the mechanism of grown-in defects (voids) formation, the succes of grown-in defect free crystal growth technology and nitrogen doped crystal are shown. New wafer fabrication technologies such as both-side mirror polishing and etchingless process have been developed. The epitaxial growth of SiGe/Si heterostructure for high speed bipolar device is treated. Gettering technology under low temperature process such as RTP is important, and also it is shown that IG effect for Ni could be predicted using computer simulation of precipitate density and size. The development of 300 mm wafer and SOI has made progress steadily.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2002년도 춘계 학술발표강연 및 논문개요집
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• pp.121-121
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• 2002

• 한국재료학회:학술대회논문집
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• 한국재료학회 1993년도 추계 학술발표 강연 및 논문 개요집
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• pp.143-144
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• 1993

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 추계학술대회 논문집 학회본부 A
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• pp.250-255
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• 2000

본 "수소 플라즈마를 이용한 SOI 기판 제작 및 SOI 전력용 반도체 소자 제작에 관한 연구"를 통해 수소플라즈마 전처리 공정에 의한 실리콘 기판 표면의 활성화를 통해 실리콘 직접 접합 공정을 수행하여 접합된 기판쌍을 제작할 수 있었으며, 접합된 기판쌍에 대한 CMP(Chemical Mechanical Polishing) 공정을 통해 SOI(Silicon on Insulator) 기판을 제작할 수 있었다. 아울러, 소자의 동작 시뮬레이션을 통해 기존 SOI LIGBT(Lateral Insulated Gate Bipolar Transistor) 소자에 비해 동작 특성이 향상된 이중 채널 SOI LIGBT 소자의 설계 파라미터를 도출하였으며, 공정 시뮬레이션을 통해 소자 제작 공정 조건을 확립하였고, 마스크 설계 및 소자 제작을 통해 본 연구 수행으로 개발된 SOI 기판의 전력용 반도체 소자 제작에 대한 가능성을 확인할 수 있었다.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2006년도 춘계학술발표대회 및 제10회 신소재 심포지엄 논문개요집
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• pp.16.1-16.1
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• 2006

• 센서학회지
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• 제19권2호
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• pp.137-141
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• 2010

In this paper, we fabricated silicon piezoresistive pressure sensor with dry etching technology which used Deep-RIE and etching delay technology which used SOI(silicon-on-insulator) wafer. We improved pressure sensor offset and its temperature dependence by removing oxidation layer of SOI wafer which was used for dry etching delay layer. Sensitivity of the fabricated pressure sensor was about 0.56 mV/V${\cdot}$kPa at 10 kPa full-scale, and nonlinearity of the fabricated pressure sensor was less than 2 %F.S. The zero off-set change rate was less than 0.6 %F.S.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1995년도 춘계학술대회 논문집
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• pp.227-229
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• 1995

Using thermal oxide SiO$_2$ as a dielectrical isolation layer, SOI Hall sensors without pn junction isolation have been fabricated on Si/SiO$_2$/Si structures. The SOI structure was formed by SDB (Si- wafer direct bonding) technology. The Hall voltage and the sensitivity of Si Hall devices implemented on the SDB SOI structure show good linearity with respect to the appled magnetic flux density and supplied current. The product sensitivity of the SDB SOI Hall device is average 600V/V.T. In the trmperature range of 25 to 300$^{\circ}C$, the shifts of TCO(Temperature Coefficient of the Offset Voltage) and TCS(Temperature Coefficient of the Product Sensitivity) are less than ${\pm}$ 6.7x10$\^$-3/ C and ${\pm}$8.2x10$\^$04/$^{\circ}C$, respectively. These results indicate that the SDB SOI structure has potential for the development of Hall sensors with a high-sensitivity and high-temperature operation.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 하계학술대회 논문집
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• pp.557-560
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• 2000

Combination of SDB(Si-wafer Direct Bonding) and electrochemical etch-stop in TMAH anisotropic etchant can be used to create a variety of MEMS(Micro Electro Mechanical System). Especially, fabrication of SDB SOI structures using electrochemical etch-stop is accurate method to fabrication of 3D(three-dimensional) microstructures. This paper describes on the fabrication of SDB SOI structures with sealed cavity for MEMS applications and thickness control of active layer on the SDB SOI structure by electrochemical etch-stop. The flatness of fabricated SDB SOI structure is very uniform and can be improved by addition of TMAH to IPA and pyrazine.

• 한국공작기계학회논문집
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• 제11권4호
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• pp.12-18
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• 2002

Silicon on insulator(SOI) wafer is used in a variety of microsensor applications in which thermal deformations and other mechanical effects may dominate device Performance. One of major Problems associated with the manufacturing Processes of the microaccelerometer based on the tunneling current concept is thermal deformations and thermal stresses. This paper deals with finite element analysis(FEA) of residual thermal deformations causing popping up, which are induced in micrormaching processes of a microaccelerometer. The reason for this Popping up phenomenon in manufacturing processes of microaccelerometer may be the bending of the whole wafer or it may come from the way the underetching occurs. We want to seek after the real cause of this popping up phenomenon and diminish this by changing manufacturing processes of mic개accelerometer. In microaccelerometer manufacturing process, this paper intend to find thermal deformation change of the temperature distribution by tunnel gap and additional beams. The thermal behaviors analysis intend to use ANSYS V5.5.3.