• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.10
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• pp.24-31
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• 2003

Short channel effects (SCE) of bulk MOSFET with super-steep retrograded channels (SSR), fully-depleted SOI, and double-gate MOSFET have been analyzed using a evanescent-mode analysis. Analytical equations of the characteristics scaling-length (λ) for three structures have been derived and the accuracy of the calculated λ was verified by comparing to the device simulation result. It is found that the minimum channel length should be larger than 5λ and the depletion thickness of the SSR should be around 30 nm in order to be applicable to 70 nm CMOS technology. High-$textsc{k}$ dielectric shows a limitation in scaling due to the drain-field penetration through the dielectric unless the equivalent SiO2 thickness is very thin.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.180-184
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• 2013

In this paper, a low power antenna switch controller IC is designed using a silicon-on-insulator (SOI) CMOS technology. To improve power handling capability and harmonic distortion performance of the antenna switch, the proposed antenna switch controller provides 3-state logic level such as +VDD, GND, and -VDD for the gate and body of switch of FETs according to decoder signal. By employing input-coupled current ring oscillator and hardware efficient level shifter, the proposed controller greatly reduces power consumption and hardware complexity. It consumes 135 ${\mu}A$ at a 2.5 V supply voltage in active mode, and occupies $1.3mm{\times}0.5mm$ in area. In addition, it shows fast start-up time of 10 ${\mu}s$.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.482-485
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• 2004

We fabricated a hybrid bulk/fully depleted silicon on insulator (FDSOI) complementary metal oxide semiconductor (CMOS) active pixel image sensor. The active pixel is comprised of reset and source follower transistors on the SOI seed wafer, while the pinned photodiode and readout gate and floating diffusion are fabricated on the SOI handle wafer after the removal of the buried oxide. The source of dark current is eliminated by hybrid bulk/FDSOI pixel structure between localized oxidation of silicon (LOCOS) and photodiode(PD). By using the low noise hybrid pixel structure, dark currents qm be suppressed significantly. The pinned photodiode can also be optimized for quantum efficiency and reduce the noise of dark current. The spectral response of the pinned photodiode on the SOI handle wafer is very flat between 400 nm and 700 nm and the dark current that is higher than desired is about 10 nA/cm2 at a $V_{DD}$ of 2 V.

• Journal of Sensor Science and Technology
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• v.11 no.5
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• pp.294-300
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• 2002

In this study, we fabricated thermopile infrared sensor with floating membrane structure. Floating membrane was formed by SOI(Silicon On Insulator) structure. In SOI structure, silicon dioxide layer between top silicon layer and bottom silicon substrate was etched by HF solution, then membrane was floated over substrate. After membrane was floated, thermopile pattern was formed on membrane. By insertion of SOI technology, we could obtain thermal isolation structure easily and passivation process for sensor pattern protection was not required during fabrication process. Then, the amplifier circuit for thermopile sensor was fabricated by using $1.5{\mu}m$ CMOS process. The voltage gain of fabricated amplifier was about two hundred.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.249-252
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• 2000

A new Smart rower IC's based on the Partial SOI technology was designed for such applications as mobile communication systems, high-speed HDD systems etc. A new methodology of integrating a 0.8${\mu}{\textrm}{m}$ BiCMOS compatible Smart Power technology, high voltage bipolar device, high speed SAVEN bipolar device, LDD NMOSFET and a new LDMOSFET based on the Partial SOI technology is presented in this paper. The high voltage bipolar device has a breakdown voltage of 40V for the output stage of analog circuit. The optimized Partial SOI LDMOSFET has an off-state breakdown voltage of 75 V and a specific on- resistance of 0.249mΩ.$\textrm{cm}^2$ with the drift region length of 3.5${\mu}{\textrm}{m}$. The high-speed SAVEN bipolar device shows cut-off frequency of about 21㎓. The simulator DIOS and DESSIS has been used to get these results.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.9
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• pp.49-53
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• 2016

A new large-signal model including the voltage-dependent extrinsic gate capacitance for RF channel distribution effect is developed for a high resistivity(HR) silicon-on-insulator(SOI) RF accumulation-mode MOS varactor. The data of voltage-dependent parameters are extracted by using accurate S-parameter optimization, and empirical model equations are constructed by data fitting process. The RF accuracy of this new model is validated by observing excellent agreements between modeled and measured Y11-parameter data in the wide voltage range up to 20 GHz.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.180-183
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• 2003

The monolayer of oxygen atoms sandwitched between the adjacent nanocrystalline silicon layers was formed by ultra high vacuum-chemical vapor deposition (UHV-CVD). This multi-layer Si-O structure forms a new type of superlattice, semiconductor-atomic superattice (SAS). According to the experimental results, high-resolution cross-sectional transmission electron microscopy (HRTEM) shows epitaxial system. Also, the current-voltage (I-V) measurement results show the stable and good insulating behavior with high breakdown voltage. It is apparent that the system may form an epitaxially grown insulating layer as possible replacement of silicon-on-insulator (SOI), a scheme investigated as future generation of high efficient and high density CMOS on SOI.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.8-22
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• 2014

In the past few decades, CMOS logic technologies and devices have been successfully developed with the steady miniaturization of the feature size. At the sub-30-nm CMOS technology nodes, one of the main hurdles for continuously and successfully scaling down CMOS devices is the parametric failure caused by random variations such as line edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV). The characteristics of each random variation source and its effect on advanced device structures such as multigate and ultra-thin-body devices (vs. conventional planar bulk MOSFET) are discussed in detail. Further, suggested are suppression methods for the LER-, RDF-, and WFV-induced threshold voltage (VTH) variations in advanced CMOS logic technologies including the double-patterning and double-etching (2P2E) technique and in advanced device structures including the fully depleted silicon-on-insulator (FD-SOI) MOSFET and FinFET/tri-gate MOSFET at the sub-30-nm nodes. The segmented-channel MOSFET (SegFET) and junctionless transistor (JLT) that can suppress the random variations and the SegFET-/JLT-based static random access memory (SRAM) cell that enhance the read and write margins at a time, though generally with a trade-off between the read and the write margins, are introduced.

• ETRI Journal
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• v.26 no.6
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• pp.575-582
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• 2004

Fully-depleted silicon-on-insulator (FD-SOI) devices with a 15 nm SOI layer thickness and 60 nm gate lengths for analog applications have been investigated. The Si selective epitaxial growth (SEG) process was well optimized. Both the single- raised (SR) and double-raised (DR) source/drain (S/D) processes have been studied to reduce parasitic series resistance and improve device performance. For the DR S/D process, the saturation currents of both NMOS and PMOS are improved by 8 and 18%, respectively, compared with the SR S/D process. The self-heating effect is evaluated for both body contact and body floating SOI devices. The body contact transistor shows a reduced self-heating ratio, compared with the body floating transistor. The static noise margin of an SOI device with a $1.1\;{\mu}m^2$ 6T-SRAM cell is 190 mV, and the ring oscillator speed is improved by 25 % compared with bulk devices. The DR S/D process shows a higher open loop voltage gain than the SR S/D process. A 15 nm ultra-thin body (UTB) SOI device with a DR S/D process shows the same level of noise characteristics at both the body contact and body floating transistors. Also, we observed that noise characteristics of a 15 nm UTB SOI device are comparable to those of bulk Si devices.

• ETRI Journal
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• v.35 no.4
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• pp.638-643
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• 2013

This paper presents a 5-bit digital step attenuator (DSA) using a commercial 0.18-${\mu}m$ silicon-on-insulator (SOI) process for the wideband phased array antenna. Both low insertion loss and low root mean square (RMS) phase error and amplitude error are achieved employing two attenuation topologies of the switched path attenuator and the switched T-type attenuator. The attenuation coverage of 31 dB with a least significant bit of 1 dB is achieved at DC to 20 GHz. The RMS phase error and amplitude error are less than $2.5^{\circ}$ and less than 0.5 dB, respectively. The measured insertion loss of the reference state is less than 5.5 dB at 10 GHz. The input return loss and output return loss are each less than 12 dB at DC to 20 GHz. The current consumption is nearly zero with a voltage supply of 1.8 V. The chip size is $0.93mm{\times}0.68mm$, including pads. To the best of the authors' knowledge, this is the first demonstration of a low phase error DC-to-20-GHz SOI DSA.