• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.1-6
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• 2002

For an optimum device design of nano-scale SOI devices, this paper describes the short channel effects of multi-gate structures SOI MOSFETs such as double gate, triple gate and quadruple gate, as well as a new proposed Pi gate using computer simulation. The simulation has been performed with different channel doping concentrations, channel widths, silicon film thickness, and vertical gate extension depths of Pi gate. From the simulation results, it is found that Pi gate devices have a large margin in determination of doping concentrations, channel widths and film thickness comparing to double and triple gate devices because Pi gate devices offer a better short channel effects.

• Proceedings of the KIEE Conference
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• 2004.07c
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• pp.1585-1587
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• 2004

이중 에피층 구조를 가지는 SOI(Silicon-On-Insulator) LIGBT(Lateral Insulated Gate Bipolar Transistor)의 에피층 두께 변화에 따른 항복전압 특성을 분석하였다. 제안된 소자는 전하보상효과를 얻기 위해 n/p-epi의 이중 에피층 구조를 사용하였으며, 에피층 전체에 걸쳐서 전류가 흐를 수 있도록 하기 위해 trenched anode구조를 채택하였다. 본 논문에서는 n/p-epi층의 농도를 고정시킨 후 각각의 epi층의 두께를 변화시켜가며 simulation을 수행하였을 때 항복전압의 변화 및 표면과 epi층에서의 전계분포변화를 분석하였다.

• Proceedings of the Materials Research Society of Korea Conference
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• 1995.11a
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• pp.23-24
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• 1995

기존의 웨이퍼 박막속에 절연박막이 삽입된 SOI(Silicon On Insulator) 웨이퍼 구조와 관련한 반도체 기판 재료가 커다른 관심을 끌어 왔으나, SOI 평가기술은 아직까지 체계적으로 확립된 것이 없으며, DLTS(Deep Level Transient Spectroscopy) 등을 이용한 전기적 평가는 거의 이루어지지 않은 상태이다. 본 연구에서는 직접접합된 웨이퍼를 약 10um내외의 활성화층을 형성시킨 6인치 P-형 SOI 웨이퍼를 제작하여 DLTS로 측정, 평가를 하였고, DLTS 측정후 관찰될 수 있는 에어지 트랩(Energy Trap)과 후속 열처리에서의 트랩의 변화등을 관찰하여, 후속 열처리조건에 따른 접합된 SOI 웨이퍼 계면의 안정화된 조건을 확보하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.05b
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• pp.301-306
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• 2000

This paper describes on the fabrication of a SOI substrate by SDB technology and electrochemical etch-stop. The surface of the thinned SDB SOI substrate is more uniform than that of grinding or polishing by mechanical method, and this process was found to be a very accurate method for SOI thickness control. During electrochemical etch-stop, leakage current versus voltage curves were measured for analysis of the open current potential(OCP) point, the passivation potential(PP) point and anodic passivation potential. The surface roughness and the controlled thickness selectivity of the fabricated a SDB SOI substrate were evaluated by using AFM and SEM, respectively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.12S
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• pp.1255-1260
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• 2003

In order to reduce driving power consumption, we propose and fabricate a new structure of asymmetric SOI 1${\times}$2 thermo-optic switch that has a back side silicon trenched structure. Compared to conventional SOI thermo optic switches without heat sink structure, it shows an improvement of switching power reduction from about 4 watt to 1.8 watt without sacrificing cross talk of about 20 ㏈ at the light wavelength of 1.55 $\mu\textrm{m}$. Here we also described the main design consideration and fabrication procedure for the proposed device.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.8
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• pp.658-662
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• 2001

This paper describes on the fabrication and characteristics of hot-film type micro-flowsensors integrated with Pt-RTD(resistance thermometer device) and micro-heater on the SOI(Si-on-insulator) membrane and trench structures, in which MGO thin-film was used as medium layer in order to improve adhesion of Pt thin-film to SiO$_2$ layer. Output voltages increased due to increase of heat-loss from sensor to external. The output voltage was 250 nV at N$_2$ flow rate of 2000 sccm/min, heating power of 0.3 W. The response time($\tau$:63%) was about 42 msec when input flow was step-input. The results indicated that micro-flowsensors with the SOI membrane and trench structures have properties of a high-resolution and ow consume power.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.53 no.6
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• pp.312-315
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• 2004

The monolayer of oxygen atoms sandwiched between the adjacent nanocrystalline silicon layers was formed by ultra high vacuum-chemical vapor deposition (UHV-CVD). This multilayer Si-O structure forms a new type of superlattice, semiconductor-atomic superlattice (SAS). According to the experimental results, high-resolution cross-sectional transmission electron microscopy (HRTEM) shows epitaxial system. Also, the current-voltage (Ⅰ-Ⅴ) measurement results show the stable and good insulating behavior with high breakdown voltage. It is apparent that the system may form an epitaxially grown insulating layer as possible replacement of silicon-on-insulator (SOI), a scheme investigated as future generation of high efficient and high density CMOS on SOI.

• Journal of the Microelectronics and Packaging Society
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• v.9 no.4
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• pp.25-29
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• 2002

We have fabricated a vertical trench Hall device which is sensitive to the magnetic field parallel to the sensor surface. The vertical trench Hall device has been built on SOI wafer which is produced by silicon direct bonding technology using bulk micromachining, where buried $SiO_2$ layer and surround trench define active device volume. Sensitivity up to 150 V/AT has been measured.

• Proceedings of the KIEE Conference
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• 2001.11a
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• pp.81-83
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• 2001

새로이 제안한 이중 애노드 LIGBT(Dual Anode LIGBT)는 빠른 스위칭을 위한 기존의 단락 애노드 구조를 캐소드의 양쪽에 위치시킴으로써 단락 애노드 구조가 갖는 부성저항영역을 효과적으로 제거했다. 뿐만 아니라 순방향전압강하 또한 기존의 분리된 단락 애노드 LIGBT (Seperate Shorted Anode LIGBT)에 비해 30%의 개선 효과를 갖는다.

• Journal of the Korean Vacuum Society
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• v.13 no.1
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• pp.1-8
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• 2004

The SOI wafer fabrication technique has been developed by using ion-cut process, based on proton implantation and wafer bonding techniques. It has been shown by TRIM simulation that 65 keV proton implantation is required for the standard SOI wafer (200 nm SOI, 400 nm BOX) fabrication. In order to investigate the optimum proton dose and primary annealing condition for wafer splitting, the surface morphologic change has been observed such as blistering and flaking. As a result, effective dose is found to be in the 6∼$9\times10^{16}$ $H^{+}/\textrm{cm}^2$ range, and the annealing at $550^{\circ}C$ for 30 minutes is expected to be optimum for wafer splitting. The depth distribution of implanted hydrogen has been experimentally confirmed by ERD and SIMS measurements. The microstructure evolution in the damaged layer was also studied by X-TEM analysis.