Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지

Device Design Guideline for Nano-scale SOI MOSFETs

나노 스케일 SOI MOSFET를 위한 소자설계 가이드라인

  • Lee, Jae-Ki (Dept. of Electronic Communication, Gachongil College) ;
  • Yu, Chong-Gun (Dept. of Electronics Engineering, Univ. of Incheon) ;
  • Park, Jong-Tae (Dept. of Electronics Engineering, Univ. of Incheon)
  • 이재기 (嘉泉吉大學 電子通信科) ;
  • 유종근 (仁天大學校 電子工學科) ;
  • 박종태 (仁天大學校 電子工學科)
  • Published : 2002.07.01
Download PDF
⟨ Previous Next ⟩

Abstract

For an optimum device design of nano-scale SOI devices, this paper describes the short channel effects of multi-gate structures SOI MOSFETs such as double gate, triple gate and quadruple gate, as well as a new proposed Pi gate using computer simulation. The simulation has been performed with different channel doping concentrations, channel widths, silicon film thickness, and vertical gate extension depths of Pi gate. From the simulation results, it is found that Pi gate devices have a large margin in determination of doping concentrations, channel widths and film thickness comparing to double and triple gate devices because Pi gate devices offer a better short channel effects.

본 연구에서는 나노 스케일 SOI 소자의 최적 설계를 위하여 multi-gate 구조인 Double 게이트, Triple 게이트, Quadruple 게이트 및 새로이 제안한 Pi 게이트 SOI 소자의 단채널 현상을 시뮬레이션을 통하여 분석하였다. 불순물 농도, 채널 폭, 실리콘 박막의 두께와 Pi 게이트를 위한 vertical gate extension 깊이 등을 변수로 하여 최적의 나노 스케일 SOI 소자는 Double gate나 소자에 비해 단채널 특성 및 subthreshold 특성이 우수하므로 채널 불순물 농도, 채널 폭 및 실리콘 박막 두께 결정에 있어서 선택의 폭이 넓음을 알 수 있었다.

Keywords

References

  1. H. S. P. Wong, D. J. Frank and P. M. Salomen, 'Device degsign considerations for double gate, ground-plane, and single-gate ultra-thin SOI MOSFETs at the 25nm channel length generation', Tech. Dig. of IEDM, pp. 98-101, 1998
  2. J. P. Colinge, X. Baie, V. Bayot, E. Grivei, 'A silicon-on-insulator quantum wire', Solid-State Electronics, Vol. 39, pp. 49-51, 1996 https://doi.org/10.1016/0038-1101(95)00094-A
  3. J. P. Colinge, M. H. Gao, A. Romano, H, Mase, and C. Claeys, 'Silicon-on-insulator gate-all-around device', Tech. Dig. of IEDM, pp. 595-598, 1990 https://doi.org/10.1109/IEDM.1990.237128
  4. C. P. Auth and J. D. Plummer, 'Scaling theory for cylindrical fully-depleted, surrounding-gate MOSFET's,' IEEE Electron Device Lett. Vol. 18, pp. 74-76, 1997 https://doi.org/10.1109/55.553049
  5. D. Hisamoto, W. C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T. J. King, J. Bokor, and C. Hu, 'FinFET-a self-alinged double-gate MOSFET scalable to 20nm,' IEEE Trans. Electron Device, Vol. 47, pp. 2320-2324, 2000 https://doi.org/10.1109/16.887014
  6. Jong Tae park, J. P. Colinge, and C. H. Diaz, 'Pi-gate SOI MOSFET,' IEEE Electron Device Lett. Vol. 22, pp. 405-406, 2001 https://doi.org/10.1109/55.936358
  7. Jong Tae Park, C. A. colinge, and J. P.Colinge, 'Comparison of gate structure for short-cahnnel SOI MOSFETs,' Proc. IEEE SOI Conf. 2001 https://doi.org/10.1109/SOIC.2001.958013
  8. G. Chindalore, S. A. Hareland, S. Jallepalli, A. F. Tasch, C. M. Maziar, V. K. F. Chia, and S. Smith, 'Experimental determination of threshold voltage shift due to quantum mechanical effects in MOS electron and hole inversion layers,' IEEE Electron Device Lett. Vol. 18, pp. 206- 208, 1997 https://doi.org/10.1109/55.568765
  9. E. Rauly, O. Potavin, F. Balestra, and C. Raynaud, 'On the suthreshold swing and short channel effects in single and double gate deep submicron SOI-MOSFETs,' Solid-State Electronics, Vol. 43, pp. 2033-2037, 1999 https://doi.org/10.1016/S0038-1101(99)00170-7