• 한국재료학회지
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• 제16권9호
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• pp.564-570
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• 2006

Silicides have been required to be below 40 nm-thick and to have low contact resistance without agglomeration at high silicidation temperature. We fabricated composite silicide layers on the wafers from Ni(20 nm)/Co(20 nm)/poly-Si(70 nm) structure by rapid thermal annealing of $700{\sim}1100^{\circ}C$ for 40 seconds. The sheet resistance, surface composition, cross-sectional microstructure, and surface roughness were investigated by a four point probe, a X-ray diffractometer, an Auger electron spectroscopy, a field emission scanning electron microscope, and a scanning probe microscope, respectively. The sheet resistance increased abruptly while thickness decreased as silicidation temperature increased. We propose that the fast metal diffusion along the silicon grain boundary lead to the poly silicon mixing and inversion. Our results imply that we may consider the serious thermal instability in designing and process for the sub-0.1 um CMOS devices.

• 제어로봇시스템학회논문지
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• 제6권1호
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• pp.104-111
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• 2000

A fuzzy logic Run-by-Run(RbR) controller and an in -line wafer characteristics prediction scheme for the rapid thermal processing system have been developed for the study of process repeatability. The fuzzy logic RbR controller provides a framework for controlling a process which is subject to disturbances such as shifts and drifts as a normal part of its operation. The fuzzy logic RbR controller combines the advantages of both fuzzy logic and feedback control. It has two components : fuzzy logic diagnostic system and model modification system. At first, a neural network model is constructed with the I/O data collected during the designed experiments. The wafer state after each run is assessed by the fuzzy logic diagnostic system with featuring step. The model modification system updates the existing neural network process model in case of process shift or drift, and then select a new recipe based on the updated model using genetic algorithm. After this procedure, wafer characteristics are predicted from the in-line wafer characteristics prediction model with principal component analysis. The fuzzy logic RbR controller has been applied to the control of Titanium SALICIDE process. After completing all of the above, it follows that: 1) the fuzzy logic RbR controller can compensate the process draft, and 2) the in-line wafer characteristics prediction scheme can reduce the measurement cost and time.

• 한국표면공학회지
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• 제38권3호
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• pp.89-94
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• 2005

We investigate the reaction stability of cobalt and nickel with side-wall materials of $SiO_2\;and\;Si_3N_4$. We deposited 15nm-Co and 15nm-Ni on $SiO_2(200nm)/p-type$ Si(100) and $Si_3N_4(70 nm)/p-type$ Si(100). The samples were annealed at the temperatures of $700\~1100^{\circ}C$ for 40 seconds with a rapid thermal annealer. The sheet resistance, shape, and composition of the residual materials were investigated with a 4-points probe, a field emission scanning electron microscopy, and an AES depth profiling, respectively. Samples of annealed above $1000^{\circ}C$ showed the agglomeration of residual metals with maze shape and revealed extremely high sheet resistance. The Auger depth profiling showed that the $SiO_2$ substrates had no residual metallic scums after $H_2SO_4$ cleaning while $Si_3N_4$ substrates showed some metallic residuals. Therefore, the $SiO_2$ spacer may be appropriate than $Si_3N_4$ for newly proposed Co/Ni composite salicide process.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2000년도 제18회 학술발표회 논문개요집
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• pp.63-63
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• 2000

Deep submicron device contact hole에서의 bottom step coverage의 향상 및 SALICIDE공정의 필요성에 의해 collimated sputtering 및 ionized sputtering 등의 다양한 증착방법이 연구되어왔다. 반도체소자의 고집적화 및 미세화에 따라서 기존의 증착방법보다 더 높은 throughput을 가진 새로운 증착방법의 필요성이 대두되고 있다. Collimated sputtering방식으로 증착한 박막의 경우에는 증착속도가 느리고 collimator의 사용기간에 따른 공정조건의 변화가 단점으로 작용하였고 새로이 ionzied sputtering방식이 개발되었다. ionzied sputtering방식은 증착되는 금속 입자를 이온화시키고 기판에 바이어스를 걸어서 증착되는 입자의 방향성 및 증착속도의 향상을 얻을 수 있었다. 하지만 고집적도가 더욱 증가함에 따라서 더 높은 박막의 증착속도, bottom step coverage의 향상, 방향성의 향상과 더불어 증착되는 입자의 이온화 율의 증가 및 기존의 증착방식에 의한 박막보다 향상된 물성을 가진 박막증착의 필요성에 의해 hollow cathode magnetron sputtering방식이 연구되었다. HCM방식으로 titanium 박막을 증착하여 collimated sputtering 및 ionize sputtering 방식으로 증착한 titanium 박막과 물성을 비교해서 증착방식에 따른 박막물성의 차이를 연구하였다. 증착전에 기판온도는 30$0^{\circ}C$를 유지하였고 base pressure는 5.0$\times$10-9torr, working pressure는 5.7m torr로 유지하였다. power는 30kW를 가하여 50nm두께의 titanium박막을 증착하였다. 증착된 박막의 미세구조는 TEM 및 XRD로 분석하였다. HCM방식으로 증착한 titanium박막은 5nm두께의 비정질 층이 관찰되었고 ionized sputtering방식으로 증착한 titatnium박막에서 나타나는 것으로 보고된 silicon (002)와 titanium (0002) eledtron diffraction spot사이의 (10-10)spot은 관찰되지 않았다. 박막은 크고 작은 grain의 연속적 분포를 가졌고 HCM방식으로 증착한 titanium박막의 in-plane grain size가 다른 증착방식으로 증착한 박막에 비해 크게 관찰됨을 Plan-view TEM 분석을 통해서 확인되었다.

• 한국재료학회지
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• 제18권1호
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• pp.5-11
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• 2008

Thermally evaporated 10 nm-Ni/1 nm-Au/(30 nm-poly)Si structures were fabricated in order to investigate the thermal stability of Au-inserted nickel silicide. The silicide samples underwent rapid thermal annealing at $300{\sim}1100^{\circ}C$ for 40 seconds. The sheet resistance was measured using a four-point probe. A scanning electron microscope and a transmission electron microscope were used to determine the cross-sectional structure and surface image. High-resolution X-ray diffraction and a scanning probe microscope were employed for the phase and surface roughness. According to sheet resistance and XRD analyses, nickel silicide with Au had no effect on widening the NiSi stabilization temperature region. Au-inserted nickel silicide on a single crystal silicon substrate showed nano-dots due to the preferred growth and a self-arranged agglomerate nano phase due to agglomeration. It was possible to tune the characteristic size of the agglomerate phase with silicidation temperatures. The nano-thick Au-insertion was shown to lead to self-arranged microstructures of nickel silicide.

• 한국표면공학회지
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• 제32권3호
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• pp.389-392
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• 1999

We employed cobalt-disilicide for high-speed logic devices. We prepared stable and low resistant $CoSi_2$ through typical fabrication process including wet cleaning and rapid thermal process (RTP). We sputtered 15nm thick cobalt on the wafer and performed RTP annealing 2 times to obtain 60nm thick $CoSi_2$. We observed spherical shape voids with diameter of 40nm in the surface and inside $CoSi_2$ layers. The voids resulted in taking over abnormal junction leakage current and contact resistance values. We report that the voids in $CoSi_2$ layers are resulted from surface pits during the ion implantation previous to deposit cobalt layer. Silicide reaction rate around pits was enhanced due to Gibbs-Thompson effects and the volume expansion of the silicidation of the flat active regime trapped dimples. We confirmed that keeping the buffer oxide layer during ion implantation and annealing the silicon surface after ion implantation were required to prevent void defects in CoSi$_2$ layers.

• 한국재료학회지
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• 제13권3호
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• pp.200-204
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• 2003

A statistical experiment method was employed to investigate the window of the thermal stability of $TiSi_2$films which are popular for Ti-salicide and ohmic layers. The statistical experimental results showed that the first order term of $TiSi_2$thickness and annealing temperature was acceptable as a function of $\Delta$resistivity by 95% reliability criteria, and R-sq value implying a fit accuracy of the model also showed a high value of 93.80%. We found that $\Delta$resistivity of the $TiSi_2$film annealed at $700^{\circ}C$ for 1 hr changed from 3.35 to $0.379\mu$$\Omega$$\cdot$cm with increasing thickness from 185 to $703\AA$, and TEX>$\Delta$resistivity of the $TiSi_2$film with a fixed thickness of 444 $\AA$ changed from 0.074 to 17.12 $\mu$$\Omega$$\cdot$cm with increasing temperature increase from 600 to $800^{\circ}C$. From these results, we report that the process conditions of$ 692^{\circ}C$-1 hr, $715^{\circ}C$-1 hr, and 73$0^{\circ}C$-1 hr for $TiSi_2$($400 \AA$) are stable by the criteria of 1, 2, and 3 $\mu$$\Omega$$\cdot$cm of $\Delta$resistivity, respectively.

• 대한전자공학회논문지SD
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• 제40권12호
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• pp.1-9
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• 2003

본 논문에서는 cobalt interlayer와 TiN capping을 적용한 Ni-Silicide 구조를 제안하여 100 ㎜ CMOS 소자에 적용하고 소자 특성 연구를 하였다. Ni-Silicide의 취약한 열 안정성을 개선하기 위해 열 안정성이 우수한 Cobalt interlayer이용하여 silicide의 열화됨을 개선하였고 또한 silicide 계면의 uniformity를 향상하기 위해 TiN capping을 동시에 적용하였다. 100 ㎚ CMOS 소자에 제안한 Co/Ni/TiN 구조를 적용하여 700℃, 30분에서의 열처리 시에도 silicide의 낮은 면저항과 낮은 접합 누설 전류가 유지되었으며 100 ㎚이하 소자의 특성 변화도 거의 없음을 확인하였다. 따라서 제안한 Co/Ni/TiN 구조가 NiSi의 열 안정성을 개선시킴으로써 100 ㎚ 이하의 Nano CNOS 소자에 매우 적합한 Ni-Silicide 특성을 확보하였다.

• 한국재료학회지
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• 제17권2호
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• pp.73-80
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• 2007

For the sub-65 nm CMOS process, it is necessary to develop a new silicide material and an accompanying process that allows the silicide to maintain a low sheet resistance and to have an enhanced thermal stability, thus providing for a wider process window. In this study, we have evaluated the property and unit process compatibility of newly proposed composite silicides. We fabricated composite silicide layers on single crystal silicon from $10nm-Ni_{1-x}Co_x/single-crystalline-Si(100),\;10nm-Ni_{1-x}Co_x/poly-crystalline-\;Si(100)$ wafers (x=0.2, 0.5, and 0.8) with the purpose of mimicking the silicides on source and drain actives and gates. Both the film structures were prepared by thermal evaporation and silicidized by rapid thermal annealing (RTA) from $700^{\circ}C\;to\;1100^{\circ}C$ for 40 seconds. The sheet resistance, cross-sectional microstructure, surface composition, were investigated using a four-point probe, a field emission scanning probe microscope, a field ion beam, an X-ray diffractometer, and an Auger electron depth profi1ing spectroscopy, respectively. Finally, our newly proposed composite silicides had a stable resistance up to $1100^{\circ}C$ and maintained it below $20{\Omega}/Sg$., while the conventional NiSi was limited to $700^{\circ}C$. All our results imply that the composite silicide made from NiCo alloy films may be a possible candidate for 65 nm-CMOS devices.

• 마이크로전자및패키징학회지
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• 제12권2호
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• pp.149-154
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• 2005

궁극적으로 게이트를 저저항 복합 실리사이드로 대체하는 가능성을 확인하기 위해 70 nm 두께의 폴리실리콘 위에 각 20nm의 Ni, Co를 열증착기로 적층순서를 달리하여 poly/Ni/Co, poly/Co/Ni구조를 만들었다. 쾌속열처리기를 이용하여 실리사이드화 열처리를 40초간 $700{\~}1100^{\circ}C$ 범위에서 실시하였다. 복합 실리사이드의 온도별 전기저항변화, 두께변화, 표면조도변화를 각각 사점전기저항측정기와 광발산주사전자현미경, 주사탐침현미경으로 확인하였다. 적층순서와 관계없이 폴리실리콘으로부터 제조된 복합실리사이드는 $800^{\circ}C$ 이상부터 급격한 고저항을 보이고, 두께도 급격히 얇아졌다. 두께의 감소는 기존의 단결정에서는 없던 현상으로 폴리실리콘의 두께가 한정된 경우 금속성분의 inversion 현상이 커서 폴리실리콘이 오히려 실리사이드 상부에 위치하여 제거되기 때문이라고 생각되었고 $1000^{\circ}C$ 이상에서는 실리사이드가 형성되지 못하였다. 이러한 결과는 나노급 두께의 게이트를 저저항 실리사이드로 만 들기 위해서는 inversion과 두께감소를 고려하여야 함을 의미하였다.