• 한국정보전자통신기술학회논문지
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• 제7권4호
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• pp.195-199
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• 2014

A bridge resistance deviation-to-period (BRD-to-P) converter is presented for interfacing resistive biosensors. It consists of a linear operational transconductance amplifier (OTA) and a current-controlled oscillator (CCO) formed by a current-tunable Schmitt trigger and an integrator. The free running period of the converter is 1.824 ms when the bridge offset resistance is $1k{\Omega}$. The conversion sensitivity of the converter amounts to $3.814ms/{\Omega}$ over the resistance deviation range of $0-1.2{\Omega}$. The linearity error of the conversion characteristic is less than ${\pm}0.004%$.

• ETRI Journal
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• 제29권1호
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• pp.70-78
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• 2007

A new low-voltage CMOS interface circuit with digital output for piezo-resistive transducer is proposed. An input current sensing configuration is used to detect change in piezo-resistance due to applied pressure and to allow low-voltage circuit operation. A simple 1-bit first-order delta-sigma modulator is used to produce an output digital bitstream. The proposed interface circuit is realized in a 0.35 ${\mu}m$ CMOS technology and draws less than 200 ${\mu}A$ from a single 1.5 V power supply voltage. Simulation results show that the circuit can achieve an equivalent output resolution of 9.67 bits with less than 0.23% non-linearity error.

• 전기전자학회논문지
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• 제23권2호
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• pp.636-641
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• 2019

저항형 센서 브리지들을 인터페이싱 하기 위한 간단한 저항 편차-시간 주기 변환기를 제안한다. 제안된 변환기는 두 개의 2세대 전류 컨베이어(current conveyor II: CCII)로 구성된다. 제안된 변환기는 연산 증폭기 또는 연산 트랜스컨덕턴스 증폭기(OTA)로 구성되는 기존의 변환기들보다 회로 구성이 간단하다는 장점을 가진다. 제안된 변환기를 AD844로 구현한 CCII를 이용하여 PSPICE 시뮬레이션을 진행하였다. 실험 결과는, 변환기가 $100{\sim}500{\Omega}$의 저항 편차 범위에 걸쳐서 $0.01934ms/{\Omega}$의 변환 감도를 가지며 선형 오차는 ${\pm}0.002%$ 이내라는 것을 보여준다.

• 한국정보전자통신기술학회논문지
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• 제7권1호
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• pp.40-44
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• 2014

저항형 바이오 센서를 인터페이싱하기 위해 브릿지 저항 편차-주기 변환기를 제안한다. 이 변환기는 선형 OTA(linear operational transconductance amplifier)와 전류-제어 발진기(current-controlled oscillator)로 구성된다. 브릿지 옵셋저항이 $1k{\Omega}$일 때, 프리러닝 주기는 1.824 ms이다. 변환기의 변 환 감도는 $0-1.2{\Omega}$의 저항편 범위에서 $3.814ms/{\Omega}$이다. 변환 특성의 선형 에러는 ${\pm}0.004%$이내이다.

• 전기전자학회논문지
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• 제12권3호
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• pp.167-171
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• 2008

저항형 센서 브리지를 인터페이싱 하기 위한 저항 편차-주파수 변환기를 제시하였다. 이 변환기는 선형 연산 트랜스컨덕턴스 증폭기(linear operational transconductance amplifier: LOTA)와 전류-제어 발진기(current-controlled oscillator: CCO)로 구성된다. 제시된 변환기를 상업용 개별 소자들을 이용하여 SPICE 시뮬레이션 하였다. 시뮬레이션 결과는, 변환기가 16.90 kHz/${\Omega}$의 변환 감도와 ${\pm}$0.03 %의 최대 선형 오차를 가진다는 것을 보여준다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 정기총회 및 창립40주년기념 학술대회 학회본부
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• pp.527-529
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• 1987

This paper presents a study on the driving characteristics or delta inverter driving induction motor control systems based on the microprocessor. Delta inverter is a novel circuit which uses only three power transistor. Requiring approximately hair the components or a conventional bridge inverter it therefore has a merit of coat and Simplicity. The basic operating principles of the delta inverter and conventional bridge inverter are argued, using resistive and inductive load. Sinusoidal PWM method uses to reduce the harmonic components of its output waveform to acceptable levels.

• Journal of Power Electronics
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• 제19권5호
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• pp.1074-1086
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• 2019

This paper presents the design and implementation of an improved cascaded multilevel inverter topology with asymmetric DC sources. This experimental inverter topology is a stand-alone system with simulations and experiments performed using resistance loads. The topology uses four asymmetric binary DC sources that are independent from each other and one H-bridge. The topology was simulated using PSIM software before an actual prototype circuit was tested. The proposed topology was shown to be very efficient. It was able to generate a smooth output waveform up to 31 levels with only eight switches. The obtained simulation and experimental results are almost identical. In a 1,200W ($48.3{\Omega}$) resistive load application, the THDv and efficiency of the topology were found to be 1.7% and 97%, respectively. In inductive load applications, the THDv values were 1.1% and 1.3% for an inductive load ($R=54{\Omega}$ dan L=146mH) and a 36W fluorescent lamp load with a capacitor connected at the dc bus.

• Journal of Power Electronics
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• 제15권3호
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• pp.741-752
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• 2015

This study proposes a new solution for the parallel operation of microgrid inverters in terms of circuit topology and control structure. A combined three-phase four-wire inverter composed of three single-phase full-bridge circuits is adopted. Moreover, the control structure is based on adaptive three-order sliding-mode control and wireless load-sharing control. The significant contributions are as follows. 1) Adaptive sliding-mode control performance in inner voltage loop can effectively reject both voltage and load disturbances. 2) Virtual resistive-output-impedance loop is applied in intermediate loop to achieve excellent power-sharing accuracy, and load power can be shared proportionally to the power rating of the inverter when loads are unbalanced or nonlinear. 3) Transient droop terms are added to the conventional power outer loop to improve dynamic response and disturbance rejection performance. Finally, theoretical analysis and test results are presented to validate the effectiveness of the proposed control scheme.