• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.461-462
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• 2008

An elaborate Simulink model for a nonredundant 10bit 20MSPS SAR ADC is proposed to verify its algorithm and to consider the real transistor-level issues of analog blocks. Some electrical trade-offs and power issues are considered.

• Agribusiness and Information Management
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• v.1 no.2
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• pp.43-60
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• 2009

To improve the performance of wide-issue superscalar processors, it is essential to increase the width of instruction fetch and the issue rate. Removal of control hazard has been put forward as a significant new source of instruction-level parallelism for superscalar processors and the conditional branch prediction is an important technique for improving processor performance. Branch mispredictions, however, waste a large number of cycles, inhibit out-of-order execution, and waste electric power on mis-speculated instructions. Hence, the branch predictor with higher accuracy is necessary for good processor performance. In global-history-based predictors like gshare and GAg, many mispredictions come from commit update of the branch history. Some works on this subject have discussed the need for speculative update of the history and recovery mechanisms for branch mispredictions. In this paper, we present a new mechanism for recovering the branch history after a misprediction. The proposed mechanism adds an age_counter to the original predictor and doubles the size of the branch history register. The age_counter counts the number of outstanding branches and uses it to recover the branch history register. Simulation results on the SimpleScalar 3.0/PISA tool set and the SPECINT95 benchmarks show that gshare and GAg with the proposed recovery mechanism improved the average prediction accuracy by 2.14% and 9.21%, respectively and the average IPC by 8.75% and 18.08%, respectively over the original predictor.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.1038-1041
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• 2005

In today's SoC design, most of IPs which use the different clock frequency from that of the bus require asynchronous FIFOs. However, in many cases, asynchronous FIFO is designed improperly and the cost of the wrong design is high. In this paper, a register-based asynchronous FIFO is designed to transfer data in asynchronous clock domains by using a valid bits scheme that eliminates the problem of the metastability and synchronization altogether. This FIFO architecture is described in HDL and synthesized to the gate level to compare with other FIFO scheme.

• Journal of the Korea Fashion and Costume Design Association
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• v.26 no.1
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• pp.33-44
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• 2024

This study developed e-book content in order to use e-books as a tool to provide more efficient classes to learners who are familiar with smart devices and online spaces. E-book contents were produced using Sigil-0.9.10. The development process is as follows. Before e-book development, it is necessary to prepare manuscript files, image files to be inserted, fonts to be used, and e-book covers. After inserting the book cover images, it is necessary to register the table of contents using the title tag and register the free fonts. Also, a style must be created for text or images used in the main text connected to a file containing the entire text. Then, after separating the entire text file into separate files according to each chapter, the text is completed in turn. E-books were produced focusing on hyperlink functions so that educational content and various example images could be accessed. Currently, there is a lack of research on e-books as textbooks in universities within the fashion design major. In the future, if e-book contents are developed according to the characteristics of courses and the level of learners, they can be used as effective teaching tools.

• Journal of information and communication convergence engineering
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• v.12 no.1
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• pp.46-52
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• 2014

This article presents key research needs in three-dimensional integrated circuit (3D IC) architectural floorplanning. Architectural floorplaning is done at a very early stage of 3D IC design process, where the goal is to quickly evaluate architectural designs described in register-transfer level (RTL) in terms of power, performance, and reliability. This evaluation is then fed back to architects for further improvement and/or modifications needed to meet the target constraints. We discuss the details of the following research needs in this article: block-level modeling, through-silicon-via (TSV) insertion and management, and chip/package co-evaluation. The goal of block-level modeling is to obtain physical, power, performance, and reliability information of architectural blocks. We then assemble the blocks into multiple tiers while connecting them using TSVs that are placed in between hard IPs and inside soft IPs. Once a full-stack 3D floorplanning is obtained, we evaluate it so that the feedback is provided back to architects.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.101-104
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• 2002

This paper propose that is algorithm of power dissipation reduction in the high level synthesis design for DSP(Digital Signal Processor), as the portable terminal system recently demand high power dissipation. This paper obtain effect of power dissipation reduction and switching activity that increase correlation of operands as input data of function unit. The algorithm search loop or repeatedly data to the input operands of function unit. That can be reduce the power dissipation using the new low power high level synthesis algorithm. In this Paper, scheduling operation search same nodes from input DFG(Data Flow Graph) with correlation coefficient of first input node and among nodes. Function units consist a multiplier, an adder and a register. The power estimation method is added switching activity for each bits of nodes. The power estimation have good efficient using proposed algorithm. This paper result obtain more Power reduction of fifty percents after using a new low power algorithm in a function unit as multiplier.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.5
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• pp.149-157
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• 1994

This paper Presents an algorithm for synthesis of sequential statements described at RT level VHDL. The proposed algorithm transforms sequential statements in VHDL into data-flow description consisting of concurrent statements by local and global dependency analysis and output dependency elimination. Transformation into concurrent statements makes it possible to reduce the cost of the synthesized hardwares, thus to get optimal synthesis results that will befit the designer 's intention. This algorithm has been implemented on VSYN and experimental results show that more compact gate-level hardwares are generated compared with Power View system from ViewLogic and Design Analyzer from Synopsys.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.246-251
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• 2006

In this paper, we introduce an implementation method of the CBS (Cycle Base Simulator), which describes the operation of a DSP (Digital Signal Processor) at a pipeline cycle level. The CBS is coded with C++, and is verified by comparing the results from the CBS and HDL simulation of the DSP with the various test vectors and application programs. The CBS shows the data about the internal registers, status flags, data bus, address bus, input and output pin of the DSP, and also the control signals at each pipeline cycle. The developed CBS can be used in evaluating the performance of the target DSP before the RTL(Register Transfer Level) coding as well as a reference for the RTL level design.

• Journal of IKEEE
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• v.18 no.4
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• pp.566-571
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• 2014

A safety class field programmable gate array based system in nuclear power plant has been developed to improve the diversity. Testbench is necessary to satisfy the technical reference, IEC-62566, for verification and validation of register transfer level code. We use the open verification methodology(OVM) developed by standard body. We show that our testbench can use random input for test. And also we show that reusability of block level testbench for the integration level testbench, which is very efficient for large scale system like nuclear reactor protection system.

• Journal of the Korea Society of Computer and Information
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• v.7 no.2
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• pp.19-33
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• 2002

In this Paper, we described the Parwan CPU using a VHDL at the behavioral level and then described by connecting CPU components at the dataflow level. Finally, we simulated to verify of execution of a CPU processor using a test-bench method. A presented design method was to enable information exchange of design and representation of operation were very exact and simple. Also. a documentation of design was available and it was easy that verify a operation of designed processor. The behavioral description of VHDL aids designer as we verify our understanding of the designed system, while the dataflow description can be used to verify the bussing and register structure of the design.