• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.9A
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• pp.2173-2183
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• 1998

We consider a frequency-hopped multiple-access communication system that employs reed-solomon code over GF(Q) and M-ary FSK signaling ($M{\leq}Q$) in rayleigh fading channel. We investigate the tradeoff among the modulation symbol size (M), the number of frequency slots, and the code rate in maximizing the average number of successfully transmitted information bits per unit time and unit bandwidth (called normalized throughput). We find that it is desirabel to use a large M in noise-limited environment. In interference-limited environment, it is more improtant to prevent errors (hits) by increasing the number of frequency slots than to correct them with formward error correction techniques or to reduce the error rate by increasing M.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.6
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• pp.1575-1582
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• 1998

Reed-Solomon(RS) code which is especially effective against burst error is studied as a forward error correction technique in this ppaer. The circuits of RS encoder and decoder for ASIC implementation are designed and presented employing modified Euclid's algorithm. The functionalities of the designed circuits are verified though C programs which simulates the circuits over the various errors and erasures. The pipelined circuits using systolic arrays are designed for ASIC realization in VHDL, and verified through the logic simulations. Finally the circuit synthesis of RS encoder and decoder can be achieved.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.5B
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• pp.966-973
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• 2000

In this paper, we propose a novel RS decoder design yielding smallr circuit size shorter coding latency. The proposed architecture of RS decoder has the following two features. First, circuit size reduced by using Euclid algorithm with mutual operation between cells. Second, coding latency is reduced by using higher frequency than syndrome and error value calculation block. We performed simulation with C language and MATLAB in order to verify the decoding algorithm and implemented using FPGA chips in VHDL.

• The Journal of the Acoustical Society of Korea
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• v.12 no.1
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• pp.20-26
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• 1993

본 논문은 Reed-Solomon부호의 복호가능어 가중치 분포에 대한 명시적 식과 근사식을 구하여 이를 복호기 오류확률 PE(u)에 적용하고, 복호기 오류확률의 상한식을 구하고 분석하였다. t+1개 이상의 오류가 발생했을 때 복호기 오류확률의 추정치 Q와 Q'를 개선하여 식 Q를 제안하고, 컴퓨터 시뮬레이션을 수행한 결과 가중치 u가 커질 때 복호기 오류확률은 추정치 Q와 Q'에는 접근하였으나, 본 논문에서 제안한 Q와는 일치됨을 확인하였다. 그리고, 가중치 u가 부호의 길이 n에 접근할 때, 복호가능어의 명시적 식 Du와 근사식 Du'가 서로 일치하고, 복호기 오류확률 Pe(u)와 근사오류확률 Pe(u')가 일치함을 보였다. 또하 t+1개 이상의 오류가 발생했을 때 복호기 오류확률은 1/t!보다 작으며, 가중치분포 Au에 Vn(t)를 곱한 결과는 근사복호가능어 Du'와 일치함도 확인하였다.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.3
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• pp.187-187
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• 2004

In this paper, we present an efficient architecture of a versatile Reed-Solomon (RS) decoder which can be programmed to decode RS codes continuously with my message length k as well as any block length n. This unique feature eliminates the need of inserting zeros for decoding shortened RS codes. Also, the values of the parameters n and k, hence the error-correcting capability t can be altered at every codeword block. The decoder permits 3-step pipelined processing based on the modified Euclid's algorithm (MEA). Since each step can be driven by a separate clock, the decoder can operate just as 2-step pipeline processing by employing the faster clock in step 2 and/or step 3. Also, the decoder can be used even in the case that the input clock is different from the output clock. Each step is designed to have a structure suitable for decoding RS codes with varying block length. A new architecture for the MEA is designed for variable values of the t. The operating length of the shift registers in the MEA block is shortened by one, and it can be varied according to the different values of the t. To maintain the throughput rate with less circuitry, the MEA block uses both the recursive technique and the over-clocking technique. The decoder can decodes codeword received not only in a burst mode, but also in a continuous mode. It can be used in a wide range of applications because of its versatility. The adaptive RS decoder over GF($2^8$) having the error-correcting capability of upto 10 has been designed in VHDL, and successfully synthesized in an FPGA chip.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.3
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• pp.29-38
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• 2004

In this paper, we present an efficient architecture of a versatile Reed-Solomon (RS) decoder which can be programmed to decode RS codes continuously with my message length k as well as any block length n. This unique feature eliminates the need of inserting zeros for decoding shortened RS codes. Also, the values of the parameters n and k, hence the error-correcting capability t can be altered at every codeword block. The decoder permits 3-step pipelined processing based on the modified Euclid's algorithm (MEA). Since each step can be driven by a separate clock, the decoder can operate just as 2-step pipeline processing by employing the faster clock in step 2 and/or step 3. Also, the decoder can be used even in the case that the input clock is different from the output clock. Each step is designed to have a structure suitable for decoding RS codes with varying block length. A new architecture for the MEA is designed for variable values of the t. The operating length of the shift registers in the MEA block is shortened by one, and it can be varied according to the different values of the t. To maintain the throughput rate with less circuitry, the MEA block uses both the recursive technique and the over-clocking technique. The decoder can decodes codeword received not only in a burst mode, but also in a continuous mode. It can be used in a wide range of applications because of its versatility. The adaptive RS decoder over GF(2$^{8}$ ) having the error-correcting capability of upto 10 has been designed in VHDL, and successfully synthesized in an FPGA chip.

• Journal of KIISE:Information Networking
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• v.33 no.4
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• pp.333-342
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• 2006

The cdma2000 lxEV - DO mobile communication system provides broadcast and multicast services (BCMCS) to meet an increasing demand from multimedia data services. The servicing of video streams over a BCMCS network must, however, face a challenge from the unreliable and error-prone nature of the radio channel. The BCMCS network uses Reed-Solomon coding integrated with the MAC protocol for error recovery. We analyze this coding technique and show that it is not effective in the case of slowly moving mobiles. To improve the playback quality of an MPEG-4 FGS video stream, we propose the Hybrid error recovery scheme, which combines Reed-Solomon with ARQ, using slots which are saved by reducing the Reed-Solomon coding overhead. The target packets to be retransmitted are prioritized by a utility function to reduce the packet error rate in the application layer within a fixed retransmission budget. This is achieved by considering of the map of the error control block at each mobile node. The proposed Hybrid error recovery scheme also uses the characteristics of MPEG-4 FGS (fine granularity scalability) to improve the video quality even when conditions are adverse: slow-moving nodes and a high error rate in the physical channel.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1998.06a
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• pp.1054-1057
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• 1998

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1996.10a
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• pp.1105-1108
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• 1996

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1998.10a
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• pp.595-598
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• 1998