• Journal of the Korean Data and Information Science Society
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• 제17권4호
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• pp.1343-1348
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• 2006

Parametric estimation of a truncated point in a right truncated Rayleigh distribution will be considered. The MLE, a bias reduced estimator and the ordinary jackknife estimator of the truncated point in the right truncated Rayleigh distribution will be compared by mean square errors. And proposed estimators of the reliability in the right truncated Rayleigh distribution will be compared by their mean squared errors.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.465-466
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• 2008

This paper shows analysis of digital correction of pipelined ADC. Sub-ADCs have some margin because of digital correction so, it can be reduced bias current for minimizing power dissipation.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
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• pp.1792-1795
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• 2007

We have proposed a new driving method which improve the current stability of a-Si:H TFTs for AMOLED. It performs the negative bias annealing on driving TFTs during a certain period of a frame time. In the proposed method, the range of data signals is significantly reduced by modulating VSS.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제50권8호
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• pp.365-370
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• 2001

We have proposed and fabricated a new poly-Si TFT employing air-cavities at the edges of gate oxide in order to reduce the vertical electric field induced near the drain due to low dielectric constant of air. Air-cavity has been successfully fabricated by employing the wet etching of gate oxide and APCVD (Atmospheric pressure chemical vapor deposition) oxide deposition. Our experimental results show that the leakage current of the proposed TFT is considerably reduced by the factor of 10 and threshold voltage shift under high gate bias is also reduced because the carrier injection into gate insulator over the drain depletion region is suppressed.

• 한국진공학회지
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• 제8권4A호
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• pp.476-481
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• 1999

Characteristics of platinum dry etching were investigated in a cryogenic magnetized inductively coupled plasma (MICP). The problem with platinum etching is the redeposition of sputtered platinum on the sidewall. Because of the redeposits on the sidewall, the etching of patterned platinum structure produces feature sizes that exceed the original dimension of the PR size and the etch profile has needle-like shape [1]. The main object of this study was to investigate a new process technology for fence-free Pt etching As bias voltage increased, the height of fence was reduced. In cryogenic etching, the height of fence was reduced to 20% at-$190^{\circ}C$ compared with that of room temperature, however the etch profile was not still fence-free. In Ar/$SF_6$ Plasma, fence-free Pt etching was possible. As the ratio of $SF_6$ gas flow is more than 14% of total gas flow, the etch profile had no fence. Chemical reaction seemed to take place in the etch process.

• Journal of Electrical Engineering and Technology
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• 제13권1호
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• pp.430-437
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• 2018

Ultrasonic attenuation is an important parameter in Quantitative Ultrasound and many algorithms have been proposed to improve estimation accuracy and repeatability for multiple independent estimates. In this work, we propose an improved algorithm for estimating ultrasonic attenuation utilizing the optimal frequency compounding technique based on stochastic noise model. We formulate mathematical compounding equations in the AWGN channel model and solve optimization problems to maximize the signal-to-noise ratio for multiple frequency components. Individual estimates are calculated by the reference phantom method which provides very stable results in uniformly attenuating regions. We also propose the guideline to select frequency ranges of reflected RF signals. Simulation results using numerical phantoms show that the proposed optimal frequency compounding method provides improved accuracy while minimizing estimation bias. The estimation variance is reduced by only 16% for the un-compounding case, whereas it is reduced by 68% for the uniformly compounding case. The frequency range corresponding to the half-power for reflected signals also provides robust and efficient estimation performance.

• 대한전자공학회논문지SD
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• 제38권4호
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• pp.251-265
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• 2001

반도체 소자가 소형화 되면서 소자의 신뢰성을 유지하고 전력 소모를 줄이기 위해 기가-비트 DRAM의 동작 전압은 1.5V 이하로 줄어들 것으로 기대된다. 따라서 기가-비트 DRAM을 구현하기 위해 저전압 회로 설계 기술이 요구된다. 이 연구에서는 지금까지 발표된 저전압 DRAM 회로 설계 기술에 대한 조사결과를 기술하였고, 기가-비트 DRAM을 위해 4가지 종류의 저전압 회로 설계 기술을 새로이 제안하였다. 이 4가지 저전압 회로 설계 기술은 subthreshold 누설 전류를 줄이는 계층적 negative-voltage word-line 구동기, two-phase VBB(Back-Bias Voltage) 발생기, two-phase VPP(Boosted Voltage) 발생기와 밴드갭 기준전압 발생기에 대한 것인데, 이에 대한 테스트 칩의 측정 결과와 SPICE 시뮬레이션 결과를 제시하였다.

• 한국지반공학회논문집
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• 제16권1호
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• pp.145-155
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• 2000

불연속면의 방향성은 암반의 과도변형이나 안정성에 영향을 미치는 특성 때문에 암반사면의 안정성 평가에 있어서 매우 중요한 역할을 한다. 불연속면의 방향측정에는 시추공(borehole)을 이용한 측정법이나 노두에서의 scanline을 이용하는 측정법과 같은 선형 측정법이 보편적으로 이용되나 이러한 측정 기법을 이용하여 획득한 자료들은 측선의 방향에 따라 쉽게 왜곡된다. 이러한 왜곡을 수정하기 위한 가중치 (weighting factor)가 적용되어도 특정 방향의 측선을 따라 자료를 획득할 경우 그 왜곡은 쉽게 보정되어지지 않는다. 즉, 불연속면의 방향자료 수집을 위해 이용된 선형 측선이 불연속면의 방향과 평행할 경우 대부분의 측선과 평행한 불연속면들은 조사 결과에 포함되지 않으며 이러한 현상은 불연속면들의 방향성 파악에 심각한 오류를 발생시킬 수 있다. 본 연구에서는 수직 측선 (borehole)에 의해 수집되어진 방향자료들과 수평 측선 (scanline)에 의해 수집되어진 방향자료들을 비교하였다. 서로 다른 두 방법에 의해 수집되어진 방향자료들은 큰 차이를 보이며, 이로 인해 불연속면들의 대표적인 방향성 결정에 장애가 되어진다. 불연속면의 경사각 분포와 수평과 수직 측선에 의해 수집되어진 자료들의 비교를 위해 등면적 극 평사투영망(polar stereo net)을 이용하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1995년도 하계학술대회 논문집 C
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• pp.1078-1080
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• 1995

The pulsed electro-acoustic method was used as a nondestructive measurement technique of spare charge distribution in dielectric materials. In our work presented here, we measured simultaneously the space charge distribution and conduction current in the low-density polyethylene samples with elevated temperatures up to $80^{\circ}C$ and electric field up to 20kV/mm. In the temperature less than $50^{\circ}C$, homocharges are mainly accumulated close to the electrodes under DC bias and after grounding. At the temperature exeeds $50^{\circ}C$, heterocharges are accumulated near the opposite electrode under DC bias. However after grounding the upper electrode, this charges immediately disappeared. The conduction current in LDPE at $20^{\circ}C$ and $30^{\circ}C$ was reduced slowly with increasing interval of applied voltage. But as temperature increased, the conduction current tended to increase slowly with the time and the degree of increase is enlarged.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권2호
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• pp.230-239
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• 2012

In this paper, we present the radio-frequency (RF) modeling for gate-all-around (GAA) junctionless (JL) MOSFETs with 30-nm channel length. The presented non-quasi-static (NQS) model has included the gate-bias-dependent components of the source and drain (S/D) resistances. RF characteristics of GAA junctionless MOSFETs have been obtained by 3-dimensional (3D) device simulation up to 1 THz. The modeling results were verified under bias conditions of linear region (VGS = 1 V, VDS = 0.5 V) and saturation region (VGS = VDS = 1 V). Under these conditions, the root-mean-square (RMS) modeling error of $Y_{22}$-parameters was calculated to be below 2.4%, which was reduced from a previous NQS modeling error of 10.2%.