• Journal of information and communication convergence engineering
• /
• v.6 no.4
• /
• pp.376-382
• /
• 2008

Developing highly cost-efficient and reliable embedded systems demands hardware/software co-design and co-simulation due to fast TTM and verification issues. So, it is essential that Platform-Based SoC design methodology be used for enhanced reusability. This paper addresses a reusable SoC platform based on OpenCores soft processor with reconfigurable architectures for hardware/software codesign methodology. The platform includes a OpenRISC microprocessor, some basic peripherals and WISHBONE bus and it uses the set of development environment including compiler, assembler, and debugger. The platform is very flexible due to easy configuration through a system configuration file and is reliable because all designed SoC and IPs are verified in the various test environments. Also the platform is prototyped using the Xilinx Spartan3 FPGA development board and is implemented to a single chip using the Magnachip cell library based on $0.18{\mu}m$ 1-poly 6-metal technology.

• Proceedings of the IEEK Conference
• /
• 1999.11a
• /
• pp.368-371
• /
• 1999

In this paper, we propose a neural network processor architecture with on-chip learning and with reconfigurability according to the data dependencies of the algorithm applied. For the neural network model applied, the proposed architecture can be configured into either SIMD or SRA(Systolic Ring Array) without my changing of on-chip configuration so as to obtain a high throughput. However, changing of system configuration can be controlled by user program. To process activation function, which needs amount of cycles to get its value, we design it by using PWL(Piece-Wise Linear) function approximation method. This unit has only single latency and the processing ability of non-linear function such as sigmoid gaussian function etc. And we verified the processing mechanism with EBP(Error Back-Propagation) model.

• Journal of Satellite, Information and Communications
• /
• v.8 no.1
• /
• pp.54-60
• /
• 2013

The need for high performance of on-board computer (OBC) is essential due to the growing requirements and diversified missions, and so OBC has been developed on the basis of the standard design and reconfigurable modularization in order to improve the utilization of OBC for different missions. The processor in OBC of next generation satellite which is currently developed by KARI is adopted the LEON2-FT/AT697F processor based SPARC v8 as main processor and controls various devices such as SpaceWire, MIL-STD-1553B and CAN through PCI on the standardized communication chips. This paper presents the architecture and design of system software for LEON2-FT processor based on PCI, and development of PCI software component. Also it describes the porting of VxWorks 6.5 for LEON2-FT and the test under the simulation environment for LEON2-FT and PCI with communication chips.

• The Transactions of the Korea Information Processing Society
• /
• v.5 no.8
• /
• pp.2027-2040
• /
• 1998

In this paper, we present efficient reconfigurable mesh algorithms for transforming between a binary image and its corresponding boundary code. These algorithms use $n\timesn\timesn$ processors when the size of the binary image is $n\timesn$. Recent published results show that these transformations can be done in O(1) time using $O(n^4)$ processors. The number of processors used by these algorithms is very large compared to the number of pixels in the image. Here, we present fast transformation algorithms which use $n^3 processors only. the transformation from a houndary code to a binary image takes O(1) time, and the converse transformation takes O(log n) time.

• Journal of the Institute of Convergence Signal Processing
• /
• v.12 no.4
• /
• pp.315-321
• /
• 2011

The CRT monitor display system for SONAR signal that are commonly used in ships or naval vessels uses vector scanning method. Therefore the processing circuits of the system is complex. Also because production had been shut down, the supply of parts is difficult as well as high-cost. FPGA -based embedded processor system is flexible to adapting to various applications because it makes simple processing circuits and its core is easily reconfigurable, and provides high speed performance in low-cost. In this paper, we describe an implementation of SONAR signal LCD display system using the FPGA embedded processor system to overcome some weakness of existing CRT system. By changing X-Y Deflection and CRT control blocks of current system into FPGA embedded processor system, our system provides the simplicity, flexibility and low-cost of system configuration, and also real-time acquisition and display of SONAR signal.

• The KIPS Transactions:PartA
• /
• v.19A no.1
• /
• pp.17-22
• /
• 2012

The demand of high performance processor is soaring due to the extending of mobile and small electronic device market. CGRA(Coarse Grained Reconfigurable Architecture) is the processor satisfying both of performance and low-power demands and a great alternative of ASIC that can be reconfigured. This paper presents a novel low-power mapping algorithm that optimizes the number of used computation resource in the mapping phase by considering data transfer time. Compared with previous mapping algorithm, ours reduce energy consumption by up to 73%, and 56.4% on average.

• Journal of KIISE:Computer Systems and Theory
• /
• v.31 no.8
• /
• pp.453-464
• /
• 2004

In order to solve the well-known drawback of reduced flexibility that is associate with ASIC implementations, this paper proposes a novel arithmetic unit over GF(2$^{m}$ ) for field programmable gate arrays (FPGAs) implementations of elliptic curve cryptographic processor. The proposed arithmetic unit is based on the binary extended GCD algorithm and the MSB-first multiplication scheme, and designed as systolic architecture to remove global signals broadcasting. The proposed architecture can perform both division and multiplication in GF(2$^{m}$ ). In other word, when input data come in continuously, it produces division results at a rate of one per m clock cycles after an initial delay of 5m-2 in division mode and multiplication results at a rate of one per m clock cycles after an initial delay of 3m in multiplication mode respectively. Analysis shows that while previously proposed dividers have area complexity of Ο(m$^2$) or Ο(mㆍ(log$_2$$^{m}$ )), the Proposed architecture has area complexity of Ο(m), In addition, the proposed architecture has significantly less computational delay time compared with the divider which has area complexity of Ο(mㆍ(log$_2$$^{m}$ )). FPGA implementation results of the proposed arithmetic unit, in which Altera's EP2A70F1508C-7 was used as the target device, show that it ran at maximum 121MHz and utilized 52% of the chip area in GF(2$^{571}$ ). Therefore, when elliptic curve cryptographic processor is implemented on FPGAs, the proposed arithmetic unit is well suited for both division and multiplication circuit.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.30B no.10
• /
• pp.1-12
• /
• 1993

A multiprocessor system for high-speed processing of hybrid image coding algorithms such as H.261, MPEG, or Digital HDTV is presented in this study. Using a combination of highly parallel 32-bit microprocessor, DCT(Discrete Cosine Transform), and motion detection processor, a new processing module is designed for the implementation of high performance coding system. The sysyem is implemented to allow parallel processing since a single module alone cannot perform hybrid coding algorithms at high speed, and crossbar switch is used to realize various parallel processing architectures by altering interconnections between processing modules within the system.

• Journal of Ubiquitous Convergence Technology
• /
• v.2 no.2
• /
• pp.59-66
• /
• 2008

In this study, Software Defined Radio (SDR) technology-based digital filterbank architecture applicable to a multiple-channel processing system such as a wireless mobile communication system using Code Division Multiple Access (CDMA) technology is proposed. The technique includes a micro-processor to redesign Finite Impulse Response (FIR) filter coefficients according to specific system information and to download the filter coefficients to one digital Band Pass Filter (BPF) to reconfigure another system. The feasibility of the algorithm is verified by computer simulation and by implementing a multiple-channel signal generator that is reconfigurable to other system profiles, including those of a Wideband Code Division Multiple Access (WCDMA) system and a CDMA system.

• Bulletin of the Korean Space Science Society
• /
• 2003.10a
• /
• pp.64-64
• /
• 2003

위성탑재용 정보 보호 토큰 처리기는 위성 운용시 관제권에 대한 제어 및 관제 데이터의 보안을 위한 코드 처리기로 위성의 명령 및 제어기의 앞단에 두어 위성의 관제를 위한 제어 코드를 관리하도록 함으로 유사시 위성 통신망의 운용을 독점하여 악의의 사용자가 위성의 관제권을 획득하지 못하도록 하기 위한 정보 보호용 토큰 처리 시스템이다. 본 정보 보호 토큰 처리기는 평상시에는 다수의 허가된 사용자가 위성망에 접근할 수 있도록 CCSDS등 표준화된 코드체계를 사용하지만, 필요 시에는 표준코드 이외에 보안 처리된 코드를 사용함으로 통신망을 보호하고 관제권을 독점할 수 있다. 정보 보호 토큰 처리기와 같은 위성 탑재용 시스템은 위성이 운용되는 우주 공간에서 보다 안정적으로 운용될 수 있도록 고 신뢰의 시스템 설계 기술이 필요하며, 본 논문에서는 우주 공간의 동작 환경 중 우주 방사선에 의한 전자회로의 동작 오류를 검출하고 정정하는 기법에 대하여 분석하고 위성에 탑재 가능한 시스템 구성을 위한 정보 보호 토큰 처리기를 설계하였다. 또한 위성의 운용 중 시스템의 보안 체계를 바꿀 수 있도록 설계하여 정보보호 토큰의 코드 노출에 대처하도록 하였다.