• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2005.11a
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• pp.500-503
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• 2005

Many researches on intelligent system have been performed and various intelligent algorithms have been developed, which are effective under an assumed specific environment and purpose. But in an real environment, the performance of these algorithms can be largely degraded. In this Paper, we Proposed an Evolvable and Reconfigurable(ERI) Architecture based on intelligent Macro Core(IMC) so that various and new algorithms can be easily added incrementally and construct the reconfigured intelligent system easily. We apply the proposed ERI Architecture to face detection and recognition system to show its usefulness.

• Journal of the Korean Institute of Intelligent Systems
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• v.15 no.7
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• pp.823-827
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• 2005

Many researches on intelligent system have been performed and various intelligent algorithms have been developed, which are effective under an assumed specific environment and purpose. But in an real environment, the Performance of these algorithms can be largely degraded. In this paper, we proposed an Evolvable and Reconfigurable(ERI) Architecture based on intelligent Macro Core(IMC) so that various and new algorithms can be easily added incrementally and construct the reconfigured intelligent system easily. We apply the proposed ERI Architecture to face detection and recognition system to show its usefulness.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.1187-1188
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• 2008

An area of research called evolvable hardware has recently emerged which combines aspects of evolutionary computation with hardware design and synthesis. Evolvable hardware (EHW) is hardware that can change its own circuit structure by genetic learning to achieve maximum adaptation to the environment. In conventional EHW, the learning is executed by software on a computer. In this paper, we have studied and surveyed a gate-level evolvable hardware chip, by integrating both GA hardware and reconfigurable hardware within a single LSI chip. The chip consists of genetic algorithm(GA) hardware, reconfigurable hardware logic, and the control logic. In this paper, we describe the architecture, functions of the chip.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1355-1360
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• 2005

In this paper, we approach the problem of image filter design automation using a kind of intrinsic evolvable hardware architecture. For the purpose of implementing the intrinsic evolution process in a common FPGA chip and evolving a complicated digital circuit system-image filter, the design automation system employs the reconfigurable circuit architecture as the reconfigurable component of the EHW. The reconfigurable circuit architecture is inspired by the Cartesian Genetic Programming and the functional level evolution. To increase the speed of the hardware evolution, the whole evolvable hardware system which consists of evolution algorithm unit, fitness value calculation unit and reconfigurable unit are implemented by a commercial FPGA chip. The Celoxica RC1000 card which is fitted with a Xilinx Virtex xcv2000E FPGA chip is employed as the experiment platform. As the result, we conclude the terms of the synthesis report of the image filter design automation system and hardware evolution speed in the Celoxica RC1000 card. The evolved image filter is also compared with the conventional image filter form the point of filtered image quality.

• 전자공학회논문지 IE
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• v.45 no.4
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• pp.27-32
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• 2008

This paper presents the implementation of simple genetic algorithm using hardware description language for evolvable hardware embedded system. Evolvable hardware refers to hardware that can change its architecture and behavior dynamically and autonomously by interacting with its environment. So, it is especially suited to applications where no hardware specifications can be given in advance. Evolvable hardware is based on the idea of combining reconfigurable hardware device with evolutionary computation, such as genetic algorithm. Because of parallel, no function call overhead and pipelining, a hardware genetic algorithm give speedup over a software genetic algorithm. This paper suggests the hardware genetic algorithm for evolvable embedded system chip. That includes simulation results for several fitness functions.

• 전자공학회논문지 IE
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• v.46 no.2
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• pp.7-10
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• 2009

This paper presents the implementation of libraries of hardware modules for genetic algorithm using VHDL. Evolvable hardware refers to hardware that can change its architecture and behavior dynamically and autonomously by interacting with its environment. So, it is especially suited to applications where no hardware specifications can be given in advance. Evolvable hardware is based on the idea of combining reconfigurable hardware device with evolutionary computation, such as genetic algorithm. Because of parallel, no function call overhead and pipelining, a hardware genetic algorithm give speedup over a software genetic algorithm. This paper suggests the hardware genetic algorithm for evolvable embedded system chip. That includes simulation results and analysis for several fitness functions. It can be seen that our design works well for the three examples.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.663-664
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• 2006

This paper presents a reconfigurable digital signal processing(rDSP) architecture that is effective for implementing adaptive digital signal processing in the applications of smart health care system. This rDSP architecture employs an evolution capability of FIR filters using genetic algorithm. Parallel genetic algorithm based rDSP architecture evolves FIR filters to explore optimal configuration of filter combination, associated parameters, and structure of feature space adaptively to noisy environments for an adaptive signal processing. The proposed DSP architecture is implemented using Xilinx Virtex4 FPGA device and SMIC 0.18um CMOS Technology.