• IEMEK Journal of Embedded Systems and Applications
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• v.2 no.4
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• pp.242-250
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• 2007

Wireless sensor networks are subject to highly heterogeneous system requirements in terms of their functionality and performance due to their broad application areas. Though the heterogeneity hinders the opportunity of developing a single universal platform for sensor networks, efforts to provide uniform, inter-operable and scalable ones for sensor networks are still essential for the growth of the industry as well as their technological advance. As a part of our work to develop such a robust platform, this paper presents the software architecture for sensor nodes with focus on our sensor node operating system and its configuration methodology. Addressing principle issues in its design space which includes programming, execution, task scheduling and software layer models, our architecture is highly reconfigurable with respect to system resources and functional requirements and also highly efficient in supporting multi-threading under small system resources.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.634-646
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• 2015

Coarse-Grained Reconfigurable Architecture (CGRA) is a very promising platform that provides fast turn-around-time as well as very high energy efficiency for multimedia applications. One of the problems with CGRAs, however, is application mapping, which currently does not scale well with geometrically increasing numbers of cores. To mitigate the scalability problem, this paper discusses how to use the SIMD (Single Instruction Multiple Data) paradigm for CGRAs. While the idea of SIMD is not new, SIMD can complicate the mapping problem by adding an additional dimension of iteration mapping to the already complex problem of operation and data mapping, which are all interdependent, and can thus significantly affect performance through memory bank conflicts. In this paper, based on a new architecture called SIMD reconfigurable architecture, which allows SIMD execution at multiple levels of granularity, we present how to minimize bank conflicts considering all three related sub-problems, for various RA organizations. We also present data tiling and evaluate a conflict-free scheduling algorithm as a way to eliminate bank conflicts for a certain class of mapping problem.

• Journal of information and communication convergence engineering
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• v.6 no.4
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• pp.376-382
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• 2008

Developing highly cost-efficient and reliable embedded systems demands hardware/software co-design and co-simulation due to fast TTM and verification issues. So, it is essential that Platform-Based SoC design methodology be used for enhanced reusability. This paper addresses a reusable SoC platform based on OpenCores soft processor with reconfigurable architectures for hardware/software codesign methodology. The platform includes a OpenRISC microprocessor, some basic peripherals and WISHBONE bus and it uses the set of development environment including compiler, assembler, and debugger. The platform is very flexible due to easy configuration through a system configuration file and is reliable because all designed SoC and IPs are verified in the various test environments. Also the platform is prototyped using the Xilinx Spartan3 FPGA development board and is implemented to a single chip using the Magnachip cell library based on $0.18{\mu}m$ 1-poly 6-metal technology.

• Journal of Platform Technology
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• v.11 no.1
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• pp.3-10
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• 2023

Unmanned Aerial Vehicles (UAVs) have gained significant attention in 5G and 6G wireless networks due to their high flexibility and low hardware costs. However, UAV communication is still challenged by blockage and energy consumption issues. Reconfigurable Intelligent Surfaces (RISs) have emerged as a promising solution to these challenges, enabling improved spectral efficiency and reduced energy consumption by transmitting signals to users who cannot receive signals because of the obstacles. Many previous studies have focused on minimizing power consumption and data transmission delay through phase shift and power optimization. This paper proposes an algorithm that maximizes the sum rate by including bandwidth optimization. Simulation results demonstrate the effectiveness of the proposed algorithm.

• Journal of Broadcast Engineering
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• v.20 no.6
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• pp.963-966
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• 2015

This paper introduces a programmable multi-format video decoder(MFD) to support HEVC(High Efficiency Video Coding) standard and for other video coding standards. The goal of the proposed MFD is the high-end FHD(Full High Definition) video decoder needed for a DTV(Digital Tele-Vision) SoC(System on Chip). The proposed platform consists of a hybrid architecture that is comprised of reconfigurable processors and flexible hardware accelerators to support the massive computational load and various kinds of video coding standards. The experimental results show that the proposed architecture is operating at a 300MHz clock that is capable of decoding HEVC bit-stream of FHD 30 frames per second.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.3B
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• pp.105-113
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• 2005

In this paper, through the implementation of the application service, we evaluated the feasibility and availability of the staged application service platform, which is based on the sharing of the PVM cluster. Application service platform provides three managers for dividing the request processing steps into two stages, such as a request processing stage and a service providing stage. Three managers and its relation to the divided stages are as follows, service manager and load manager to distribute the request in front-end server for a request processing stage, job manager in clustered(back-end) servers for a service providing stage. The experiment shows that the staged application service platform provides more stable and scalable characteristics and better performance improvement on the dynamic load changes than the single server system. And also it shows that real application service system can be implemented easily without modification of the proposed service platform.

• Journal of Korea Multimedia Society
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• v.12 no.5
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• pp.617-632
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• 2009

In this paper we propose a technique of implementing the reconfigurable network protocol stack that allows for partitioning network protocol functions into software and hardware tasks on a SoC (System on Chip) platform. Additionally, we present a method that guarantees the deadline of both an individual task and messages exchanging among tasks in order to meet the deadline of real-time multimedia and networking services. The proposed real-time message exchange method guarantees the deadline of messages generated by multimedia services that are required to meet the real-time properties of multimedia applications. After implementing the networking functions of TCP/IP protocol suite into hardware and software tasks, we verify and validate their performance on the SoC platform. Experimental results indicate that the proposed technique improves the performance of TCP/IP protocol suit as well as application service satisfaction in application-specific real-time.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.06a
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• pp.163-165
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• 2014

In this paper, we propose a world's first programmable video processing platform for video quality enhancement of 8K ($7680{\times}4320$) UHD (Ultra High Definition) TV at 60 frames per second. To support huge computation and memory bandwidth of video quality enhancement for 8K resolution, the proposed platform has unique features like symmetric multi-cluster architecture for data partitioning, ring data-path between clusters to support data pipelining, on-the-fly processing architecture to reduce DDR bandwidth, flexible hardware to accelerating common kernel in video enhancement algorithms. In addition to those features, general programmability of SRP (Samsung reconfigurable processor) as main core of the proposed platform makes it possible to upgrade continuously video enhancement algorithm even after the platform is fixed. This ability is very important because algorithms for 8K DTV is under development. The proposed sub-system has been embedded into SoC (System on Chip) and new 8K UHD TV using the programmable SoC is expected at CES2015 for the first time in the world.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.11
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• pp.949-958
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• 2016

This paper presents the new development result of the multi-band, the multi-mode SDR(Software Defined Radar) platform. The SDR hardware platform is implemented by using the reconfigurable multi-band RF transceiver and antenna modules of S, X, and K-bands, and a programmable signal processing module. The SDR software platform is implemented by using the multi-mode waveform generation of CW, Pulse, FMCW, and LFM Chirp as well as the adaptable algorithm library of signal processing and open API software modules. Through the integrated test of the SDR platform, the operational performance was verified in real-time. Also, through the field-application test, the ground target and air-vehicle drone target were successfully detected and their test results were presented.

• Journal of IKEEE
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• v.17 no.4
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• pp.407-417
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• 2013

In this paper, a reconfigurable peripheral unit for LED lighting communication is presented. Embedded lighting devices require various communication protocols. Usually, serial communication protocols and lighting control communication protocols such as DALI, DMX512, UART, SPI, IrDA, etc. are used in lighting devices. When the requirements of communication protocols are satisfied with separate IPs, the cost and the power consumption can considerably increase. We propose a reconfigurable communication peripheral unit which uses analysis of signal formats of the protocols. The gate count of the reconfigurable peripheral unit uses only 57% of the gate count of the separate implementation. Also, in this paper, a mapping table based DALI-ZigBee interfacing method for flexible lighting network configurations is proposed. Using this method, various DALI-ZigBee network systems can be easily set up. An LED lighting system platform is implemented to verify the operation of the DALI-ZigBee interfacing method. The reconfigurable peripheral unit and the DALI-ZigBee interfacing method can be efficiently used to implement various wired/wireless lighting communication systems.