• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.12
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• pp.1112-1115
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• 2015

Recently, there have been advancements in radar related material technology, circuit design techniques and architecture design techniques. These have led to developments in radars' performance while decreasing the costs. Many studies have been carried out to apply radars to multipurpose application. In this study, a reconfigurable S-/X- band radar structure for multipurpose application is proposed and implemented. This radar measures a $51.2cm{\times}50.6cm$ target for 10 times from 2 m to 6 m range with 0.25 m distance step. The measured results show that this radar has 26.40 cm maximum range error, 5.63 cm average range error, and 0.24 cm range error variance at S-band while it has 8.53 cm maximum range error, 2.52 cm average range error, and 0.04 cm range error variance at X-band.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.740-743
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• 2008

RSA crypto-processors equipped with more than 1024 bits of key space handle the entire key stream in units of blocks. The RSA processor which will be the target design in this paper defines the length of the basic word as 128 bits, and uses an 256-bits register as the accumulator. For efficient execution of 128-bit multiplication, $32b^*32b$ multiplier was designed and adopted and the results are stored in 8 separate 128-bit registers according to the stalks flag. In this paper, a fast 32bit nodular multiplier which is required to execute 128-bit MAC (multiplication and accumulation) operation is proposed. The proposed architecture prototype of the multiplier unit was automatically synthesized, and successfully operated at the frequency in the target RSA processor.

• 전자공학회논문지 IE
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• v.46 no.2
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• pp.7-10
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• 2009

This paper presents the implementation of libraries of hardware modules for genetic algorithm using VHDL. Evolvable hardware refers to hardware that can change its architecture and behavior dynamically and autonomously by interacting with its environment. So, it is especially suited to applications where no hardware specifications can be given in advance. Evolvable hardware is based on the idea of combining reconfigurable hardware device with evolutionary computation, such as genetic algorithm. Because of parallel, no function call overhead and pipelining, a hardware genetic algorithm give speedup over a software genetic algorithm. This paper suggests the hardware genetic algorithm for evolvable embedded system chip. That includes simulation results and analysis for several fitness functions. It can be seen that our design works well for the three examples.

• 전자공학회논문지 IE
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• v.45 no.4
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• pp.27-32
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• 2008

This paper presents the implementation of simple genetic algorithm using hardware description language for evolvable hardware embedded system. Evolvable hardware refers to hardware that can change its architecture and behavior dynamically and autonomously by interacting with its environment. So, it is especially suited to applications where no hardware specifications can be given in advance. Evolvable hardware is based on the idea of combining reconfigurable hardware device with evolutionary computation, such as genetic algorithm. Because of parallel, no function call overhead and pipelining, a hardware genetic algorithm give speedup over a software genetic algorithm. This paper suggests the hardware genetic algorithm for evolvable embedded system chip. That includes simulation results for several fitness functions.

• Journal of Broadcast Engineering
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• v.24 no.1
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• pp.182-185
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• 2019

This paper analyzes performances of modules in implementing a programmable multi-format video decoder. The goal of the proposed platform is the high-end Full High Definition (FHD) video decoder. The proposed multi-format video decoder consists of a reconfigurable processor, dedicated bit-stream co-processor, memory controller, cache for motion compensation, and flexible hardware accelerators. The experiments suggest performance baseline of modules for the proposed architecture operating at 300 MHz clock with capability of decoding HEVC bit-streams of FHD 30 frames per second.

• Journal of Internet Computing and Services
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• v.6 no.4
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• pp.21-35
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• 2005

Software product-lines is the software development paradigm to attain the rapid development of quality applications by customizing the reconfigurable components and composing them based on predefined software architectures. Recently various methodologies for the component-based product lines are proposed, but these don't provide the specific implementation techniques of the components in terms of variability resolution mechanism. In other hand, the several approaches to implement the component supporting the variabilities resolution are developed, but these don't define the systematic analysis and design method considering the variabilities from the initial phase. This paper proposes the integration of PLUS, the one of product line methodologies extending UML modeling, and component code generation technique in order to increase the efficiency of producing the specific product in the software product lines. In this paper, the component has the hierarchical architecture consisting of the implementation elements, and each implementation elements are implemented as XSLT scripts. The codes of the components are generated from the feature selection. Using the microwave oven product lines as case study, the development process for the reconfigurable components supporting the automatic variability resolution is described.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.3
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• pp.106-111
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• 2011

This paper presents an ASIP (Application-specific Instruction Processor) for motion estimation that employs specific IME instructions and its programmable and reconfigurable hardware architecture for various video codecs, such as H.264/AVC, MPEG4, etc. With the proposed specific instructions and hardware accelerator, it can handle the real-time processing requirement of High Definition (HD) video. With the parallel operations and SAD unit control using pattern information, the proposed IME instruction supports not only full search algorithm but also other fast search algorithms. The hardware size is 77K gates for each Processing Element Group (PEG) which has 256 SAD PEs. The proposed ASIP runs at 160MHz with sixteen PEGs and it can handle 1080p@30 frame in real time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.58-65
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• 2011

This paper presents an ASIP (Application-specific Instruction Processor) for motion estimation that employs specific IME instructions and its programmable and reconfigurable hardware architecture for various video codecs, such as H.264/AVC, MPEG4, etc. With the proposed specific instructions and variable point 2D SAD hardware accelerator, it can handle the real-time processing requirement of High Definition (HD) video. With the SAD unit and its parallel operations using pattern information, the proposed IME instructions support not only full search algorithms but also other fast search algorithms. The hardware size is 25.5K gates for each Processing Element Group (PEG) which has 128 SAD Processor Elements (PEs). The proposed ASIP has been verified by the Synopsys Processor Designer and implemented by the Design Compiler using the IBM 90nm process technology. The hardware size is 453K gates for the IME unit and the operating frequency is 188MHz for 1080p@30 frame in real time. The proposed ASIP can reduce the hardware size about 26% and the number of operation cycles about 18%.

• Journal of the Korea Society for Simulation
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• v.19 no.4
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• pp.179-188
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• 2010

The concern of Software Product Line(SPL) engineering is spreading widely because the program or product developers are able to satisfy the customer's demands quickly and give a way to handle maintenance efficiently. SPL is a reuse paradigm that reuse common parts and adopts variable parts optionally to form a differentiated product by analyzing domains. Purposes of this paper are to design an architecture which has a dynamic reconfiguration function and to develop basic components which are the basic unit of reconfiguration to raise the reuse level of the guided weapon system using the SPL. Initially we design an architecture and define basic components for developing a dynamic reconfigurable components based on SPL. Then we develop the composer for physical components and behavior components referenced by behavior models of OneSAF.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.368-371
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• 1999

In this paper, we propose a neural network processor architecture with on-chip learning and with reconfigurability according to the data dependencies of the algorithm applied. For the neural network model applied, the proposed architecture can be configured into either SIMD or SRA(Systolic Ring Array) without my changing of on-chip configuration so as to obtain a high throughput. However, changing of system configuration can be controlled by user program. To process activation function, which needs amount of cycles to get its value, we design it by using PWL(Piece-Wise Linear) function approximation method. This unit has only single latency and the processing ability of non-linear function such as sigmoid gaussian function etc. And we verified the processing mechanism with EBP(Error Back-Propagation) model.