• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.506-507
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• 2007

Lateral Information Propagation Neural Networks (LIPN) is proposed for on-line interpolation. The proposed neural network technique is the real time computation method through the inter-node diffusion. In the network, a node corresponds to a state in the quantized input space. Through several simulation experiments, real time reconstruction of the nonlinear image information is processed.

• Proceedings of the KIEE Conference
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• 2007.11c
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• pp.83-87
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• 2007

Correlation Propagation Neural Networks is proposed for On-line interpolation. The proposed neural network technique is the real time computation method through the inter-node diffusion. In the network, a node corresponds to a state in the quantized input space. Each node is composed of a processing unit and fixed weights from its neighbor nodes as well as its input terminal. Information propagates among neighbor nodes laterally and inter-node interpolation is achieved. Through several simulation experiments, real time reconstruction of the nonlinear image information is processed. 1-D CPNN hardware has been implemented with general purpose analog ICs to test the interpolation capability of the proposed neural networks. Experiments with static and dynamic signals have been done upon the CPNN hardware.

• Proceedings of the KIEE Conference
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• 1998.07b
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• pp.461-464
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• 1998

Lateral Information Propagation Neural Networks (LIPN) is proposed for on-line interpolation. The proposed neural network technique is the real time computation method through the inter-node diffusion. In the network, a node corresponds to a state in the quantized input space. Each node is composed of a processing unit and fixed weights from its neighbor nodes as well as its input terminal. Information propagates among neighbor nodes laterally and inter-node interpolation is achieved. Through several simulation experiments, real time reconstruction of the nonlinear image information is processed. 1-D LIPN hardware has been implemented with general purpose analog ICs to test the interpolation capability of the proposed neural networks. Experiments with static and dynamic signals have been done upon the LIPN hardware.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2001.04a
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• pp.405-410
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• 2001

In this paper, a new parametric curve interpolator is proposed based on a 3D(3-dimensional) NURBS curve. A free curve is generally divided into small linear segments or circular arcs in CNC machining. The method has caused to a command error, the limitation of machining speed, and the irregular machining surface. The proposed real-time 3D NURBS interpolator continuously generates a linear segment within the range of allowable acceleration/deceleration in the motion controller. Therefore, the algorithm calculates the curvature and the remained distance of a command curve for the smoothing machining. It is expected to attaining high speed and high precision machining in CNC Machine Tool.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2001.04a
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• pp.399-404
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• 2001

In CNC machining, a 3D(3-dimension) linear segment and a 2D(2-dimension) circular arc are general forms given by CAD/CAM system. Generally, the 2D circular arc machining is processed using dividing into some linear segments. A 3D circular arc also don't exist in the standard form of NC data. This paper present a algorithm and method for real-time machining of a circular arc(not only the 2D one, but also the 3D one). The 3D circular arc machining is based on the 2D circular arc machining. It only needs making a new coordinate system, converting given 3D points(a start point, a end point, and a center point of a 3D circular arc) into points of the new coordinate system, and processing a inverse transformation about a interpolated point. The proposed algorithm was implemented and simulated on PC system. It was confirmed to give a gcod result.

• Journal of IKEEE
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• v.28 no.1
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• pp.26-32
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• 2024

Recently, various video resolution formats have emerged, and digital devices have built in dedicated scaler chips to support them by enlarging or reducing the resolution of input videos. Therefore, the performance and hardware size of scaler chips are important. In this paper, the combinatorial interpolation scaler algorithm proposed by Han is used to design the hardware using the line memory structure with dual-clock proposed by Han and Jung. The proposed hardware is capable of real-time processing in QHD environments, designed using Verilog, and validated using Xilinx's Vivado 2023.1. We also verify the performance of Han's proposed algorithm with a quantitative numerical evaluation of the proposed hardware.

• Journal of the Korean Society for Precision Engineering
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• v.16 no.9
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• pp.172-178
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• 1999

3D linear and circular interpolations are a basic part for the machining of complex shapes. Until now, because of the absence of appropriate algorithms for the generation of 3D lines and circles, a full accomplishment for available machine tool resolution is difficult. this paper presents new algorithms for 3D linear and circular interpolation in the reference pulse technique. In 3D space, the line or circle is not expressed as an implicit function, it is only defined as the intersection of two surfaces. A 3D line is defined as the intersection of two planes, and a 3D circle is defined as the intersection of a plane and the surface of a sphere. Based on these concepts, interpolation algorithms are designed to follow intersection curves in 3D space, and a real-time 3D linear and circular interpolator was developed in software using a PC. The algorithm implemented in a PC showed promising results in interpolation error and speed performance. It is expected that it can be applied to the next generation computerized numerical control systems for the machining of 3D lines, circles and some other complex shapes.

• Journal of Auto-vehicle Safety Association
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• v.13 no.2
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• pp.35-41
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• 2021

In this study, improved path tracking control algorithm based on pure pursuit algorithm is newly proposed by using improved lane detection algorithm through real time post-processing with interpolation methodology. Since the original pure pursuit works well only at speeds below 20 km/h, the look-ahead distance is implemented as a sigmoid function to work well at an average speed of 45 km/h to improve tracking performance. In addition, a smoothing filter was added to reduce the steering angle vibration of the original algorithm, and the stability of the steering angle was improved. The post-processing algorithm presented has implemented more robust lane recognition system using real-time pre/post processing method with deep learning and estimated interpolation. Real time processing is more cost-effective than the method using lots of computing resources and building abundant datasets for improving the performance of deep learning networks. Therefore, this paper also presents improved lane detection performance by using the final results with naive computer vision codes and pre/post processing. Firstly, the pre-processing was newly designed for real-time processing and robust recognition performance of augmentation. Secondly, the post-processing was designed to detect lanes by receiving the segmentation results based on the estimated interpolation in consideration of the properties of the continuous lanes. Consequently, experimental results by utilizing driving guidance line information from processing parts show that the improved lane detection algorithm is effective to minimize the lateral offset error in the diverse maneuvering roads.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.58 no.4
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• pp.511-515
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• 2009

For detecting of the faulty insulator, Correlation Propagation Neural Networks(CPNN) has been proposed. Faulty insulator is reduced the rate of insulation extremely, and taken the results dirty and injured. It is necessary to detect the faulty insulator and exchange the new one. And thus, we have designed the CPNN to be detected that insulators by the real time computation method through the inter-node diffusion. In the network, a node corresponds to a state in the quantized input space. Each node is composed of a processing unit and fixed weights from its neighbor nodes as well as its input terminal. Information propagates among neighbor nodes laterally and inter-node interpolation is achieved. 1-D CPNN hardware has been implemented with general purpose. Experiments with static and dynamic signals have been done upon the CPNN hardware. Through the results of simulation experiments, we define the ability of real-time detecting the faulty insulators.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.6
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• pp.91-100
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• 2016

In FPGA-based real-time image warping systems, image caches are utilized for fast readout of image pixel data and reduction of memory access rate. However, a cache algorithm for a general computer system is not suitable for real-time performance because of time delays from cache misses and on-line computation complexity. In this paper, a simple image cache algorithm is presented for a FPGA-based real-time image warping system. Considering that pixel data access sequence is determined from the 2D coordinate transformation and repeated identically at every image frame, a cache load sequence is off-line programmed to guarantee no cache miss condition, and reduced on-line computation results in a simple cache controller. An overall system structure using a FPGA is presented, and experimental results are provided to show accuracy and validity of the proposed cache algorithm.