• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.506-507
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• 2007

Lateral Information Propagation Neural Networks (LIPN) is proposed for on-line interpolation. The proposed neural network technique is the real time computation method through the inter-node diffusion. In the network, a node corresponds to a state in the quantized input space. Through several simulation experiments, real time reconstruction of the nonlinear image information is processed.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 학술대회 논문집 전문대학교육위원
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• pp.83-87
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• 2007

Correlation Propagation Neural Networks is proposed for On-line interpolation. The proposed neural network technique is the real time computation method through the inter-node diffusion. In the network, a node corresponds to a state in the quantized input space. Each node is composed of a processing unit and fixed weights from its neighbor nodes as well as its input terminal. Information propagates among neighbor nodes laterally and inter-node interpolation is achieved. Through several simulation experiments, real time reconstruction of the nonlinear image information is processed. 1-D CPNN hardware has been implemented with general purpose analog ICs to test the interpolation capability of the proposed neural networks. Experiments with static and dynamic signals have been done upon the CPNN hardware.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 하계학술대회 논문집 B
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• pp.461-464
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• 1998

Lateral Information Propagation Neural Networks (LIPN) is proposed for on-line interpolation. The proposed neural network technique is the real time computation method through the inter-node diffusion. In the network, a node corresponds to a state in the quantized input space. Each node is composed of a processing unit and fixed weights from its neighbor nodes as well as its input terminal. Information propagates among neighbor nodes laterally and inter-node interpolation is achieved. Through several simulation experiments, real time reconstruction of the nonlinear image information is processed. 1-D LIPN hardware has been implemented with general purpose analog ICs to test the interpolation capability of the proposed neural networks. Experiments with static and dynamic signals have been done upon the LIPN hardware.

• 한국공작기계학회:학술대회논문집
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• 한국공작기계학회 2001년도 춘계학술대회 논문집(한국공작기계학회)
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• pp.405-410
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• 2001

In this paper, a new parametric curve interpolator is proposed based on a 3D(3-dimensional) NURBS curve. A free curve is generally divided into small linear segments or circular arcs in CNC machining. The method has caused to a command error, the limitation of machining speed, and the irregular machining surface. The proposed real-time 3D NURBS interpolator continuously generates a linear segment within the range of allowable acceleration/deceleration in the motion controller. Therefore, the algorithm calculates the curvature and the remained distance of a command curve for the smoothing machining. It is expected to attaining high speed and high precision machining in CNC Machine Tool.

• 한국공작기계학회:학술대회논문집
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• 한국공작기계학회 2001년도 춘계학술대회 논문집(한국공작기계학회)
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• pp.399-404
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• 2001

In CNC machining, a 3D(3-dimension) linear segment and a 2D(2-dimension) circular arc are general forms given by CAD/CAM system. Generally, the 2D circular arc machining is processed using dividing into some linear segments. A 3D circular arc also don't exist in the standard form of NC data. This paper present a algorithm and method for real-time machining of a circular arc(not only the 2D one, but also the 3D one). The 3D circular arc machining is based on the 2D circular arc machining. It only needs making a new coordinate system, converting given 3D points(a start point, a end point, and a center point of a 3D circular arc) into points of the new coordinate system, and processing a inverse transformation about a interpolated point. The proposed algorithm was implemented and simulated on PC system. It was confirmed to give a gcod result.

• 전기전자학회논문지
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• 제28권1호
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• pp.26-32
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• 2024

최근 다양한 영상의 해상도 포맷이 등장하였고, 디지털 기기는 이를 지원하기 위해 입력 영상의 해상도를 확대 또는 축소하는 전용 스케일러 칩을 내장하고 있다. 따라서 스케일러 칩의 성능과 하드웨어 크기는 중요하다고 할 수 있다. 본 논문에서는 Han이 제안한 조합 보간 스케일러 알고리즘을 Han, Jung이 제안한 Dual-clock을 가지는 라인 메모리 구조를 이용해 하드웨어 설계를 진행하였다. 제안하는 하드웨어는 QHD 환경에서 실시간으로 처리가 가능한 구조로, Verilog를 이용해 설계되었으며 Xilinx Vivado 2023.1을 이용하여 검증하였다. 또한 Han이 제안한 알고리즘과 하드웨어의 정량적 수치 평가 비교를 통해 성능을 검증하였다.

• 한국정밀공학회지
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• 제16권9호
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• pp.172-178
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• 1999

3D linear and circular interpolations are a basic part for the machining of complex shapes. Until now, because of the absence of appropriate algorithms for the generation of 3D lines and circles, a full accomplishment for available machine tool resolution is difficult. this paper presents new algorithms for 3D linear and circular interpolation in the reference pulse technique. In 3D space, the line or circle is not expressed as an implicit function, it is only defined as the intersection of two surfaces. A 3D line is defined as the intersection of two planes, and a 3D circle is defined as the intersection of a plane and the surface of a sphere. Based on these concepts, interpolation algorithms are designed to follow intersection curves in 3D space, and a real-time 3D linear and circular interpolator was developed in software using a PC. The algorithm implemented in a PC showed promising results in interpolation error and speed performance. It is expected that it can be applied to the next generation computerized numerical control systems for the machining of 3D lines, circles and some other complex shapes.

• 자동차안전학회지
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• 제13권2호
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• pp.35-41
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• 2021

In this study, improved path tracking control algorithm based on pure pursuit algorithm is newly proposed by using improved lane detection algorithm through real time post-processing with interpolation methodology. Since the original pure pursuit works well only at speeds below 20 km/h, the look-ahead distance is implemented as a sigmoid function to work well at an average speed of 45 km/h to improve tracking performance. In addition, a smoothing filter was added to reduce the steering angle vibration of the original algorithm, and the stability of the steering angle was improved. The post-processing algorithm presented has implemented more robust lane recognition system using real-time pre/post processing method with deep learning and estimated interpolation. Real time processing is more cost-effective than the method using lots of computing resources and building abundant datasets for improving the performance of deep learning networks. Therefore, this paper also presents improved lane detection performance by using the final results with naive computer vision codes and pre/post processing. Firstly, the pre-processing was newly designed for real-time processing and robust recognition performance of augmentation. Secondly, the post-processing was designed to detect lanes by receiving the segmentation results based on the estimated interpolation in consideration of the properties of the continuous lanes. Consequently, experimental results by utilizing driving guidance line information from processing parts show that the improved lane detection algorithm is effective to minimize the lateral offset error in the diverse maneuvering roads.

• 전기학회논문지P
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• 제58권4호
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• pp.511-515
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• 2009

For detecting of the faulty insulator, Correlation Propagation Neural Networks(CPNN) has been proposed. Faulty insulator is reduced the rate of insulation extremely, and taken the results dirty and injured. It is necessary to detect the faulty insulator and exchange the new one. And thus, we have designed the CPNN to be detected that insulators by the real time computation method through the inter-node diffusion. In the network, a node corresponds to a state in the quantized input space. Each node is composed of a processing unit and fixed weights from its neighbor nodes as well as its input terminal. Information propagates among neighbor nodes laterally and inter-node interpolation is achieved. 1-D CPNN hardware has been implemented with general purpose. Experiments with static and dynamic signals have been done upon the CPNN hardware. Through the results of simulation experiments, we define the ability of real-time detecting the faulty insulators.

• 전자공학회논문지
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• 제53권6호
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• pp.91-100
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• 2016

FPGA 기반 실시간 영상 워핑 시스템에서는 영상 픽셀 정보의 빠른 읽기와 메모리 접근 횟수의 감소를 위하여 영상 캐시를 활용하지만, 일반 컴퓨터 시스템의 캐시 알고리즘은 캐시 부적중(cache miss)에 의한 시간 지연과 복잡한 온라인(on-line) 연산 구조로 인하여 실시간 성능 구현에 어려움이 있다. 본 논문에서는 FPGA 기반 실시간 영상 워핑을 위한 단순한 구조의 영상 캐시 알고리즘을 제안한다. 영상 워핑에서의 픽셀 데이터 접근 순서는 워핑에 적용할 2D 좌표변환 관계에 의하여 결정되며 매 영상 프레임에서 반복되는 특성이 있다. 따라서, 캐시 로드(cache load)에 관한 사항을 오프라인(off-line)에서 미리 프로그램함으로써 캐시 부적중 상황이 발생하지 않음을 보장할 수 있고, 그 결과 온라인에서의 연산이 감소하여 캐시 컨트롤러의 구조가 단순해진다. FPGA를 활용한 전체 시스템 구조를 제시하고, 실험을 통하여 제안하는 영상 캐시 알고리즘의 정확성과 타당성을 확인한다.