• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.46-52
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• 2009

A Multi-Core/Multi-Thread architecture is adopted for the Shader processor to enhance the processing performance. The Shader processor is designed to utilize its processing core IP for multiple purposes, such as Vertex-Shading, Rasterization, Pixel-Shading, etc. In this paper, we propose a 'Rasterization based on Vector Algorithm' that makes parallel pixels processing possible with Multi-Core and Multi-Thread architecture on the Shader Core. The proposed algorithm takes only 2% operation counts of the Scan-Line Algorithm and processes pixels independently.

• Cartoon and Animation Studies
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• s.36
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• pp.493-510
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• 2014

From game consoles to TV and Hollywood films, 3D rendering technology is involved in various fields. Up until the late 90s, the computer image rendering method was rasterization that mainly used Phong Shading, and up until recently it was the go-to method for movies and film animation. In the 21st century, the quality provided by Ray Tracing and the development of Global Illumination was much more realistic and thus became popularized. However, despite its growing use in architectural rendering to the markets, Global Illumination in film animation and movies was limited due to its long render time. So, in this thesis, if one were to take the concept from each rendering method and consider it from a mathematical perspective, one could adapt the Ambient Occlusion's equation to the illumination loop equation used in rasterization. This algorithm modification has the capability to reflect the lighting of a diverse array of colors, like in Global Illumination, with a fast render time, as in rasterization, and the example RenderMan Shader is based upon this new algorithm. In conclusion, with Global Illumination's naturalistic lighting and rasterization's rendering speed, the combination of the best points of each is a new method with a short rendering time while producing good quality. I hope animations and films can benefit from this algorithm by the reduction of budget with an overall better quality output in VFX production.

• IEMEK Journal of Embedded Systems and Applications
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• v.8 no.2
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• pp.87-93
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• 2013

In this paper, we implemented and evaluated the performance of a vector-based rasterization algorithm of 3D graphics using a SIMD-based many-core processor that consists of 4,096 processing elements. In addition, we compared the performance and efficiency of the rasterization algorithm using the many-core processor and commercial GPU (Graphics Processing Unit) system which consists of 7 GPUs and each of which have 512 cores. Experimental results showed that the SIMD-based many-core processor outperforms the commercial GPU system in terms of execution time (3.13x speedup), energy efficiency (17.5x better), and area efficiency (13.3x better). These results demonstrate that the SIMD-based many-core processor has potential as an embedded mobile processor.

• Proceedings of the Korea Information Processing Society Conference
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• 2013.05a
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• pp.140-143
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• 2013

본 논문에서는 데이터 병렬성이 뛰어난 벡터 기반의 Rasterization 알고리즘을 CUDA를 이용하여 코어 매핑에 따른 성능 및 에너지 효율을 분석해 보았다. 블록 사이즈를 동일하게 맞춘 후 블록의 차원을 변경 하는 방법과 블록 사이즈를 변경하는 방법을 사용하여 실험하였다. 모의실험결과, 블록 사이즈가 동일할 때는 오차 범위 내로 동일한 성능과 에너지 효율을 보였다. 아키텍처마다 모든 자원을 사용할수 있는 이론적인 블록 및 스레드 구조가 존재하지만 메모리 접근에 대한 최적화를 이루어 내지 못한다면 Amdahl's law에 의해 성능 향상에 한계가 있다는 것을 확인하였다.

• IEMEK Journal of Embedded Systems and Applications
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• v.9 no.1
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• pp.17-24
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• 2014

In this paper, we implement and evaluate the performance of a vector-based rasterization algorithm for 3D graphics by using a SIMD (single instruction multiple data) many-core processor architecture. In addition, we evaluate the impact of a data-per-processing elements (DPE) ratio that is defined as the amount of data directly mapped to each processing element (PE) within many-core in terms of performance, energy efficiency, and area efficiency. For the experiment, we utilize seven different PE configurations by varying the DPE ratio (or the number PEs), which are implemented in the same 130 nm CMOS technology with a 500 MHz clock frequency. Experimental results indicate that the optimal PE configuration is achieved as the DPE ratio is in the range from 16,384 to 256 (or the number of PEs is in the range from 16 and 1,024), which meets the requirements of mobile devices in terms of the optimal performance and efficiency.

• Journal of IKEEE
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• v.20 no.1
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• pp.75-81
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• 2016

This paper proposes a design of the tile based on graphic pipeline to improve the graphic application performance in SIMT based GP-GPU. The proposed Tile based on graphics pipeline avoids unnecessary graphic processing operation, and processes the rasterization step in parallel. The massive data processing in parallel through SIMT architecture improve the computational performance, thereby improving the 3D graphic pipeline performance. The more vertex data of 3D model, the higher performance. The proposed structure was confirmed to improve processing performance of up to 3 times from about 1.18 times as compared to 'RAMP' and previous studies.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1492-1494
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• 1987

This paper describes a hardware architecture called Edge Painting Machine for real time generation of scan line images for raster scan graphics display. The Edge Painting Machine consists of Scanline Processor which converts polygon data sorted in their depth priority into a set of scan line commands for each scan line, and Edge Painting Tree which converts the scanline commands set into a raster line image. Edge painting tree has been designed using combinational logic circuit. The designed circuit has been simulated to verify the proper functioning. A salient feature of the EPT is that hardware composition is simple, because each processor is constituted by only combinational logic circuit.

• Journal of IKEEE
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• v.13 no.2
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• pp.253-259
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• 2009

In this paper, we propose a novel architecture of a general graphics shader processor without a dedicated hardware. Recently, mobile devices require the high performance graphics processor as well as the small size, low power. The proposed shader processor is a GP-GPU(General-Purpose computing on Graphics Processing Units) to execute the whole OpenGL ES 2.0 graphics pipeline by using shader instructions. It does not require the separate dedicate H/W such as rasterization on this fully programmable capability. The fully programmable 3D graphics shader processor can reduce much of the graphics hardware. The chip size of the designed shader processor is reduced 60% less than the sizes of previous processors.

• Journal of the Korean Institute of Landscape Architecture
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• v.27 no.4
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• pp.137-142
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• 1999

The purpose of this study is to develope a CAD-based tool for rasterization of polygonal vector map in AutoCAD. To identity the layer property of polygonal entity with user-defined coordinates as topology, algorithm in processing entity data of selection set that intersected with scan line was used, and the layers were extracted sequentially by sorted intersecting points in data-list. In addition to the functions for querying and modifying topology, two options for mapping were set up to construct plan projection type and to change meshes' properties in existing DTM data. In case of plan projection type, user-defined cell size of 3DFACE mesh is available for more detailed edge, and topological draping on landform can be executed in case of referring DTM data as an AutoCAD's drawing. The concept of algorithm was simple and clear, but some unexpectable errors were found in detecting intersected coordinates that were AutoCAD's error, not the utility's. Also, the routines to check these errors were included in algorithmic processing. Developed utility named MESHMAP was written in entity data control functions of AutoLISP language and dialog control language(DCL) for the purpose of user-oriented interactive usage. MESHMAP was proved to be more effective in data handling and time comparing with GRIDMAP module in LANDCADD which has similar function.

• Proceedings of the Korean Information Science Society Conference
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• 2002.04a
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• pp.25-27
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• 2002

본 논문에서는 3차원 그래픽의 래스터라이제이션 단계에서 발생하는 메모리 트래픽 문제를 해결하기 위해 사용되는 텍스처 및 픽셀 캐쉬에 대한 성능을 분석하였다. 이를 위해 화면의 해상도, 컬러 정보, 깊이 정보 및 캐쉬 구성의 변화에 따른 이들 캐쉬의 성능변화를 살펴보았으며 실험결과 텍스처 캐쉬와 픽셀 캐쉬의 설계 시에 블록 크기에 의한 영향이 매우 중요함을 알 수 있었다. 특히 픽셀 캐쉬의 경우에는 시간적 지역성은 거의 없으며 매우 큰 공간적 지역성을 보이므로 이를 잘 반영할 수 있는 캐쉬 구조가 필요하다.