• Korean Journal of Materials Research
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• v.12 no.10
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• pp.820-824
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• 2002

It is of importance to know that the bonding strength and interfacial stress of SOI wafer pairs to meet with mechanical and thermal stresses during process. We fabricated Si/2000$\AA$-SiO$_2$ ∥ 2000$\AA$-SiO$_2$/Si SOI wafer pairs with electric furnace annealing, rapid thermal annealing (RTA), and fast linear annealing (FLA), respectively, by varying the annealing temperatures at a given annealing process. Bonding strength and interfacial stress were measured by a razor blade crack opening method and a laser curvature characterization method, respectively. All the annealing process induced the tensile thermal stresses. Electrical furnace annealing achieved the maximum bonding strength at $1000^{\circ}C$-2 hr anneal, while it produced constant thermal tensile stress by $1000^{\circ}C$. RTA showed very small bonding strength due to premating failure during annealing. FLA showed enough bonding strength at $500^{\circ}C$, however large thermal tensile stress were induced. We confirmed that premated wafer pairs should have appropriate compressive interfacial stress to compensate the thermal tensile stress during a given annealing process.

• Mass Spectrometry Letters
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• v.7 no.4
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• pp.91-95
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• 2016

In recent years, matrix-free laser desorption ionization (LDI) for mass spectrometry of thermally labile molecules has been an important research subject in the pursuit of new ionization methods to serve as alternatives to the conventional matrix-assisted laser desorption ionization (MALDI) method. While many recent studies have reported successful LDI of thermally labile molecules from various surfaces, mostly from surfaces with nanostructures, understanding of what drives the LDI process still requires further study. This article briefly reviews the thermal aspects involved in the LDI mechanism, which can be characterized as rapid surface heating. The thermal mechanism was supported by observed LDI and postsource decay (PSD) of peptide ions produced from flat surfaces with special thermal properties including amorphous Si (a-Si) and tungsten silicide ($WSi_x$). In addition, the concept of rapid surface heating further suggests a practical strategy for the preparation of LDI sample plates, which allows us to choose various surface materials including crystalline Si (c-Si) and Au tailorable to specific applications.

• Korean Journal of Materials Research
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• v.24 no.9
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• pp.443-450
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• 2014

Amorphous (a-Si) films were epitaxially crystallized on a very thin large-grained poly-Si seed layer by a silicide-enhanced rapid thermal annealing (SERTA) process. The poly-Si seed layer contained a small amount of nickel silicide which can enhance crystallization of the upper layer of the a-Si film at lower temperature. A 5-nm thick poly-Si seed layer was then prepared by the crystallization of an a-Si film using the vapor-induced crystallization process in a $NiCl_2$ environment. After removing surface oxide on the seed layer, a 45-nm thick a-Si film was deposited on the poly-Si seed layer by hot-wire chemical vapor deposition at $200^{\circ}C$. The epitaxial crystallization of the top a-Si layer was performed by the rapid thermal annealing (RTA) process at $730^{\circ}C$ for 5 min in Ar as an ambient atmosphere. Considering the needle-like grains as well as the crystallization temperature of the top layer as produced by the SERTA process, it was thought that the top a-Si layer was epitaxially crystallized with the help of $NiSi_2$ precipitates that originated from the poly-Si seed layer. The crystallinity of the SERTA processed poly-Si thin films was better than the other crystallization process, due to the high-temperature RTA process. The Ni concentration in the poly-Si film fabricated by the SERTA process was reduced to $1{\times}10^{18}cm^{-3}$. The maximum field-effect mobility and substrate swing of the p-channel poly-Si thin-film transistors (TFTs) using the poly-Si film prepared by the SERTA process were $85cm^2/V{\cdot}s$ and 1.23 V/decade at $V_{ds}=-3V$, respectively. The off current was little increased under reverse bias from $1.0{\times}10^{-11}$ A. Our results showed that the SERTA process is a promising technology for high quality poly-Si film, which enables the fabrication of high mobility TFTs. In addition, it is expected that poly-Si TFTs with low leakage current can be fabricated with more precise experiments.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.10
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• pp.840-846
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• 1991

In case of the rapid thermal process by halogen lamps, an optical pyrometer is generally used to measure the temperature. It is, however, necessary to measure the temperature by the thermocouple when the process temperature is lower than 700$^{\circ}C$ and the correction of the temperature is required. Contact by the PdAg paste is commonly used out but in this case it is impossible to see the effect of surface states of the substrate, which is critical in the rapid thermal process. In this study, real temperature ramping speed of silicon substrates coveredwith various thin films such as SiO$_2$2, Si$_{3}N_{4}$, dopants, and conductive layers (Ti or Co) was investigated by a mechanical contact of the thermocouple. And the results were compared with the case in which the contact was made by the PdAg paste. Effect of process ambient was also studied. It was found that depending on the surface state, overshoot more than 100$^{\circ}C$ could occur. It was also found that in case of the substrate covered with conductive layers, mechanical contact might render the correct temperature.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.29 no.2
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• pp.50-53
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• 2019

In this study, polycrystalline silicon thin film useful for the solar cells was fabricated by AIC(Aluminum Induced Crystallization) process. A diffusing barrier for this process is prepared with $Al_2O_3$. For the maximization of the grain size of the polycrystalline silicon, a selective blasting of the $Al_2O_3$ diffusing barrier was conducted before annealing treatment. The heat treatment for the activation of the amorphous-Si (a-Si) layer was carried out with Rapid Thermal Annealing (RTA) process. Crystallization of the a-Si layer was analyzed with XRD. It was confirmed that a-Si was crystallized at $500^{\circ}C$ and the silicon crystal is observed to be formed and the grain size of the polycrystalline silicon was observed to be $15.9{\mu}m$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.3
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• pp.236-240
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• 2012

Limiting thermal exposure time using rapid thermal processing(RTP) has emerged as promising simplified process for manufacturing of solar cell in a continuous way. This paper reports the simplification of co-firing using RTP. Actual temperature profile for co-firing after screen printing is a key issue for high-quality metal-semiconductor contact. The plateau time during the firing process were varied at $450^{\circ}C$ for 10~16 sec. Glass frit in Ag paste etch anti-reflection layer with plateau time. Glass frit in Ag paste is important for the Ag/Si contact formation and performances of crystalline Si solar cell. We achieved 17.14% efficiency with optimum conditions.

• Journal of Institute of Control, Robotics and Systems
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• v.5 no.4
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• pp.481-488
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• 1999

A thermal model based on the chamber geometry of the industry-standard AST SHS200MA rapid thermal processing system has been developed for the study of thermal uniformity and process repeatability thermal model combines radiation energy transfer directly from the tungsten-halogen lamps and the steady-state thermal conducting equations. Because of the difficulties of solving partial differential equation, calculation of wafer temperature was performed by using finite-difference approximation. The proposed thermal model was verified via titanium silicidation experiments. As a result, we can conclude that the thermal model show good estimation of wafer surface temperature distribution.

• Journal of the Semiconductor & Display Technology
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• v.23 no.1
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• pp.88-91
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• 2024

The europium doped yttrium oxide (Y₂O₃:Eu³⁺) thin film was formed on a Si substrate by the conventional spin-coating process followed by rapid thermal annealing (RTA) treatment. The spinning profiles such as rotation speed, acceleration and holding times were controlled during the spin-coating process for the best condition of the Y₂O₃:Eu³⁺ thin film. The RTA treatment was conducted for several temperature in order to crystallize the spin coated film. The Y₂O₃:Eu³⁺ thin film presented best performance in the conditions of 4000 rpm, 30 s and 10 s of rotation speed, acceleration time and holding time, respectively, at a fixed RTA temperature of 900 ℃.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.5
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• pp.410-414
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• 2013

Rapid thermal processing (RTP) abruptly decreases the time required to perform solar cell processes. RTP were used to form emitter of crystalline silicon solar cells. The emitter sheet resistance is studied as a function of time and temperature. The objective of this study is reduction of doping process time with same performance. Emitter difRapid thermal dfusion was carried out by using a spin on doping and a RTP. iffusion was performed in the temperature range of $700{\sim}750^{\circ}C$ for 1m 30s~15 m. Thermal budgets yielded a $50{\Omega}/sq$ emitter using a P509 source. To reduce process time and get high efficiency, rapid thermal diffusion by IR lamp was employed in air atmosphere at $700^{\circ}C$ for 15 m.

• Journal of Institute of Control, Robotics and Systems
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• v.6 no.1
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• pp.104-111
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• 2000

A fuzzy logic Run-by-Run(RbR) controller and an in -line wafer characteristics prediction scheme for the rapid thermal processing system have been developed for the study of process repeatability. The fuzzy logic RbR controller provides a framework for controlling a process which is subject to disturbances such as shifts and drifts as a normal part of its operation. The fuzzy logic RbR controller combines the advantages of both fuzzy logic and feedback control. It has two components : fuzzy logic diagnostic system and model modification system. At first, a neural network model is constructed with the I/O data collected during the designed experiments. The wafer state after each run is assessed by the fuzzy logic diagnostic system with featuring step. The model modification system updates the existing neural network process model in case of process shift or drift, and then select a new recipe based on the updated model using genetic algorithm. After this procedure, wafer characteristics are predicted from the in-line wafer characteristics prediction model with principal component analysis. The fuzzy logic RbR controller has been applied to the control of Titanium SALICIDE process. After completing all of the above, it follows that: 1) the fuzzy logic RbR controller can compensate the process draft, and 2) the in-line wafer characteristics prediction scheme can reduce the measurement cost and time.