• Title/Summary/Keyword: RTA annealing

Search Result 391, Processing Time 0.029 seconds

Effect of Annealing on the Dielectric Properties and Microstructures of Thin Tantalum Oxide Film Deposited with RF Reactive Sputtering

  • Lee, Gyeong-Su;Nam, Kee-Soo;Chun, Chang-Hwan;Kim, Geun-Hong
    • ETRI Journal
    • /
    • v.13 no.2
    • /
    • pp.21-27
    • /
    • 1991
  • Effects of annealing on the dielectric properties and microstructures of thin tantalum oxide film(25nm) deposited on p-type Si substrate with rf reactive magnetron sputtering were investigated. The leakage current density was remarkably reduced from $10^-8$ to $10^-12$ A/$\mum^2$at the electric field of 2MV/cm after rapid thermal annealing(RTA) in $O_2$at $1000^{\circ}C$, while little leakage reduction was observed after furnace annealing in $O_2$ at $500^{\circ}C$. The structural changes of thin tantalum oxide film after annealing were examined using high resolution electron microscope(HREM). The results of HREM show that substantial reduction in the leakage current density after the RTA in $O_2$ can be attributed to crystallization and reoxidation of the thin amorphous tantalum oxide film.

  • PDF

Stress Evolution with Annealing Methods in SOI Wafer Pairs (열처리 방법에 따른 SOI 기판의 스트레스변화)

  • Seo, Tae-Yune;Lee, Sang-Hyun;Song, Oh-Sung
    • Korean Journal of Materials Research
    • /
    • v.12 no.10
    • /
    • pp.820-824
    • /
    • 2002
  • It is of importance to know that the bonding strength and interfacial stress of SOI wafer pairs to meet with mechanical and thermal stresses during process. We fabricated Si/2000$\AA$-SiO$_2$ ∥ 2000$\AA$-SiO$_2$/Si SOI wafer pairs with electric furnace annealing, rapid thermal annealing (RTA), and fast linear annealing (FLA), respectively, by varying the annealing temperatures at a given annealing process. Bonding strength and interfacial stress were measured by a razor blade crack opening method and a laser curvature characterization method, respectively. All the annealing process induced the tensile thermal stresses. Electrical furnace annealing achieved the maximum bonding strength at $1000^{\circ}C$-2 hr anneal, while it produced constant thermal tensile stress by $1000^{\circ}C$. RTA showed very small bonding strength due to premating failure during annealing. FLA showed enough bonding strength at $500^{\circ}C$, however large thermal tensile stress were induced. We confirmed that premated wafer pairs should have appropriate compressive interfacial stress to compensate the thermal tensile stress during a given annealing process.

Effect of annealing on the properties of zinc doped indium oxide(IZO) films (후열처리에 따른 Indium Zinc Oxide(IZO) 박막의 특성변화)

  • Kim, Dae-Hyun;Kim, Sang-Mo;Choi, Hyung-Wook;Kim, Kyung-Hwan;Rim, You-Seong
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
    • /
    • 2008.11a
    • /
    • pp.260-261
    • /
    • 2008
  • In this study, we investigated the properties of Indium Zinc Oxide (IZO) films prepared in facing targets sputtering (FTS) system at room temperature as function of oxygen contents. As as-deposited films were rapidly thermal annealing on air atmosphere of $400^{\circ}C$ for 30s. As a result, the transmittance of IZO films increased with increasing oxygen flow in the visible range. After rapidly thermal annealing to films, the optical properties of films improved than films deposited at R.T, but the electrical properties decreased. Before RTA treatment, the lowest resistivity IZO is $5.4\times10^{-4}[\Omega{\cdot}cm]$ at oxygen gas flow. But, after RTA treatment, IZO films have the value of lowest resistivity at the lower oxygen gas ratio in compare with before RTA treatment. The resistivity of IZO films is $7.29\times10^{-4}[\Omega{\cdot}cm]$ at pure argon atmosphere.

  • PDF

A study on the design of boron diffusion simulator applicable for shallow $p^+-n$ junction formation (박막 $p^+-n$ 접합 형성을 위한 보론 확산 시뮬레이터의 제작에 관한 연구)

  • Kim, Jae-Young;Kim, Bo-Ra;Hong, Shin-Nam
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
    • /
    • 2004.04b
    • /
    • pp.30-33
    • /
    • 2004
  • Shallow p+-n junctions were formed by low-energy ion implantation and dual-step annealing processes The dopant implantation was performed into the crystalline substrates using $BF_2$ ions. The annealing was performed with a rapid thermal processor and a furnace. FA+RTA annealing sequence exhibited better junction characteristics than RTA+FA thermal cycle from the viewpoint of junction depth. A new simulator is designed to model boron diffusion in silicon, which is especially useful for analyzing the annealing process subsequent to ion implantation. The model which is used in this simulator takes into account nonequilibrium diffusion, reactions of point defects, and defect-dopant pairs considering their charge states, and the dopant inactivation by introducing a boron clustering reaction. Using a resonable parameter values, the simulator covers not only the equilibrium diffusion conditions but also the nonequilibrium post-implantation diffusion. Using initial conditions and boundary conditions, coupled diffusion equation is solved successfully. The simulator reproduced experimental data successfully.

  • PDF

A Study on the Shallow $p^+-n$ Junction Formation and the Design of Diffusion Simulator for Predicting the Annealing Results ($p^+-n$ 박막접합 형성방법과 열처리 모의 실험을 위한 시뮬레이터 개발에 관한 연구)

  • Kim, Bo-Ra;Lee, Jae-Young;Lee, Jeong-Min;Hong, Shin-Nam
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
    • /
    • 2005.07a
    • /
    • pp.115-117
    • /
    • 2005
  • In this paper, we formed the shallow junction by preamorphization and low energy ion implantation. And a simulator is designed for predicting the annealing process results. Especially, if considered the applicable to single step annealing process(RTA, FA) and dual step annealing process(RTA+FA, FA+RTA). In this simulation, the ion implantation model and the boron diffusion model are used. The Monte Carlo model is used for the ion implantation. Boron diffusion model is based on pair diffusion at nonequilibrium condition. And we considered that the BI-pairs lead the diffusion and the boron activation and clustering reaction. Using the boundary condition and initial condition, the diffusion equation is solved successfully. The simulator is made ofC language and reappear the experimental data successfully.

  • PDF

Microwave Annealing을 이용한 MOS Capacitor의 특성 개선

  • Jo, Gwang-Won;Jo, Won-Ju
    • Proceedings of the Korean Vacuum Society Conference
    • /
    • 2013.08a
    • /
    • pp.241.1-241.1
    • /
    • 2013
  • 최근 고집적화된 금속-산화막 반도체 metal oxide semiconductor (MOS) 소자는 크기가 점점 작아짐에 따라 얇은 산화막과 다양한 High-K 물질과 전극에 대하여 연구되고 있다. 이러한 소자의 열적 안정성과 균일성을 얻기 위해 다양한 열처리 방법이 사용되고 있으며, 일반적인 열처리 방법으로는 conventional thermal annealing (CTA)과 rapid thermal annealing (RTA)이 많이 이용되고 있다. 본 실험에서는 microwave radiation에 의한 열처리로 소자의 특성을 개선시킬 수 있다는 사실을 확인하였고, 상대적으로 $100^{\circ}C$ 이하의 저온에서도 공정이 이루어지기 때문에 열에 의한 소자 특성의 열화를 억제할 수 있으며, 또한 짧은 처리 시간 및 공정의 단순화로 비용을 효과적으로 절감할 수 있다. 본 실험에서는 metal-oxide-silicon (MOS) 구조의 capacitor를 제작한 다음, 기존의 CTA나 RTA 처리가 아닌 microwave radiation을 실시하여 MOS capacitor의 전기적인 특성에 미치는 microwave radiation 효과를 평가하였다. 본 실험은 p-type Si 기판에 wet oxidation으로 300 nm 성장된 SiO2 산화막 위에 titanium/aluminium (Ti/Al) 금속 전극을 E-beam evaporator로 형성하여 capacitance-voltage (C-V) 특성 및 current-voltage (I-V) 특성을 평가하였다. 그 결과, microwave 처리를 통해 flat band voltage와 hysteresis 등이 개선되는 것을 확인하였고, microwave radiation 파워와 처리 시간을 최적화하였다. 또한 일반적인 CTA 열처리 소자와 비교하여 유사한 전기적 특성을 확인하였다. 이와 같은 microwave radiation 처리는 매우 낮은 온도에서 공정이 이루어짐에도 불구하고 시료 내에서의 microwave 에너지의 흡수가 CTA나 RTA 공정에서의 열에너지 흡수보다 훨씬 효율적으로 이루어지며, 결과적으로 산화막과 실리콘 기판의 계면 특성 개선에 매우 효과적이라는 것을 나타낸다. 따라서, microwave radiation 처리는 향후 저온공정을 요구하는 nano-scale MOSFET의 제작 및 저온 공정이 필수적인 display 소자 제작의 해결책으로 기대한다.

  • PDF

Effects of rapid thermal annealing on indium-zinc-oxide films (산화인듐아연 박막에 대한 급속 열처리 효과)

  • Kim, Won;Uhm, Hyun-Seok;Bang, Jung-Hwan;Park, Jin-Seok
    • Proceedings of the KIEE Conference
    • /
    • 2009.07a
    • /
    • pp.1268_1269
    • /
    • 2009
  • This work shows the effect of rapid thermal annealing (RTA) on properties of indium-zinc oxide (IZO) thin films. The RTA temperatue was controlled between 300 and $500^{\circ}C$ under the two different ambient conditions such as vacuum and oxygen. Structural, optical, and electrical properties of IZO films were characterized in terms of RTA conditions. XRD and resistivity measurements showed that crystallization for IZO films occurred at an RTA temperature of about $400^{\circ}C$. For the IZO film treated at $500^{\circ}C$ of RTA, the resistivity, carrier concentration, hall mobility, and transmittance were approximately $10^2{\Omega}cm$, $10^{15}cm^{-3}$, $10cm^2/V{\cdot}s$, and 85%, respectively, which would be suitable for its application to the channel layer in transparent thin film transistors.

  • PDF

The characterization for the Ti-silicide of $N^+P$ junction by 2 step RTD (2단계 RTD방법에 의한 $N^+P$ 접합 티타늄 실리사이드 특성연구)

  • 최도영;윤석범;오환술
    • Electrical & Electronic Materials
    • /
    • v.8 no.6
    • /
    • pp.737-743
    • /
    • 1995
  • Two step RTD(Rapid Thermal Diffussion) of P into silicon wafer using tungsten halogen lamp was used to fabricated very shallow n$^{+}$p junction. 1st RTD was performed in the temperature range of 800.deg. C for 60 see and the heating rate was in the 50.deg. C/sec. Phosphrous solid source was transfered on the silicon surface. 2nd RTD process was performed in the temperature range 1050.deg. C, 10sec. Using 2 step RTD we can obtain a shallow junction 0.13.mu.m in depth. After RTD, the Ti-silicide process was performed by the two step RTA(Rapid Thermal Annealing) to reduced the electric resistance and to improve the n$^{+}$p junction diode. The titanium thickness was 300.angs.. The condition of lst RTA process was 600.deg. C of 30sec and that of 2nd RTA process was varied in the range 700.deg. C, 750.deg. C, 800.deg. C for 10sec-60sec. After 2 step RTA, sheet resistance was 46.ohm../[]. Ti-silicide n+p junction diode was fabricated and I-V characteristics were measured.red.

  • PDF

Se-loss-induced CIS Thin Films in RTA Process after Co-sputtering Using CuSe2 and InSe2 Targets

  • Kim, Nam-Hoon;Jun, Young-Kil;Cho, Geum-Bae
    • Journal of Electrical Engineering and Technology
    • /
    • v.9 no.3
    • /
    • pp.1009-1015
    • /
    • 2014
  • Chalcopyrite $CuInSe_2$ (CIS) thin films were prepared without Se- / S-containing gas by co-sputtering using $CuSe_2$ and $InSe_2$ selenide-targets and rapid thermal annealing. The grain size increased to a maximum of 54.68 nm with a predominant (112) plane. The tetragonal distortion parameter ${\eta}$ decreased and the inter-planar spacing $d_{(112)}$ increased in the RTA-treated CIS thin films annealed at a $400^{\circ}C$, which indicates better crystal quality. The increased carrier concentration of RTA-treated p-type CIS thin films led to a decrease in resistivity due to an increase in Cu composition at annealing temperatures ${\geq}350^{\circ}C$. The optical band gap energy ($E_g$) of CIS thin films decreased to 1.127 eV in RTA-treated CIS thin films annealed at $400^{\circ}C$ due to the improved crystallinity, elevated carrier concentration and decreased In composition.

Screen printed contacts formation by rapid thermal annealing in multicrystalline silicon solar cells

  • Kim, Kyung hae;U. Gangopadhyay;Han, Chang-Soo;K. Chakrabarty;J. Yi
    • Journal of Korean Vacuum Science & Technology
    • /
    • v.6 no.3
    • /
    • pp.120-125
    • /
    • 2002
  • The aim of the present work is to optimized the annealing parameter in both front and back screen printed contacts realization on p-type multicrystalline silicon and with phosphorus diffused. The RTA treatments were carried out at various temperatures from 600 to 850$\^{C}$ and annealing time ranging from 3 min to 5 min in air, O$_2$and N$_2$ ambiance. The contacts parameters are obtained according to Transmission Line Model measurements. A good RTA cycle is obtained with a temperature plateau of 700$\^{C}$-750$\^{C}$ and annealing ambiance of air. Several processing parameters required for good cell efficiency are discussed with an emphasis placed on the critical role of the glass frit in the aluminum paste. A anamolus behaviour of Aluminum n-doping on p-type Si wafer, contact at high temperature have also been studied.

  • PDF