• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.3
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• pp.684-690
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• 2010

Most of the existing SoCs have shared bus architecture which always has a bottleneck state. The more IPs are in an SOC, the less performance it is of the SOC, Therefore, its performance is effected by the entire communication rather than CPU speed. In this paper, we propose cross-bar switch bus architecture for the reduction of the bottleneck state and the improvement of the performance. The cross-bar switch bus supports up to 8 masters and 16 slaves and parallel communication with architecture of multiple channel bus. Each slave has an arbiter which stores priority information about masters. So, it prevents only one master occupying one slave and supports efficient communication. We compared WISHBONE on-chip shared bus architecture with crossbar switch bus architecture of the SOC platform, which consists of an OpenRISC processor, a VGA/LCD controller, an AC97 controller, a debug interface, a memory interface, and the performance improved by 26.58% than the previous shared bus.

• KIPS Transactions on Computer and Communication Systems
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• v.11 no.6
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• pp.167-174
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• 2022

PIPO lightweight block ciphers were announced in ICISC'20. In this paper, a single-block optimization implementation and parallel optimization implementation of PIPO lightweight block cipher ECB, CBC, and CTR operation modes are performed on a 32-bit RISC-V processor. A single block implementation proposes an efficient 8-bit unit of Rlayer function implementation on a 32-bit register. In a parallel implementation, internal alignment of registers for parallel implementation is performed, and a method for four different blocks to perform Rlayer function operations on one register is described. In addition, since it is difficult to apply the parallel implementation technique to the encryption process in the parallel implementation of the CBC operation mode, it is proposed to apply the parallel implementation technique in the decryption process. In parallel implementation of the CTR operation mode, an extended initialization vector is used to propose a register internal alignment omission technique. This paper shows that the parallel implementation technique is applicable to several block cipher operation modes. As a result, it is confirmed that the performance improvement is 1.7 times in a single-block implementation and 1.89 times in a parallel implementation compared to the performance of the existing research implementation that includes the key schedule process in the ECB operation mode.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.431-441
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• 2003

This paper presents the design of 32 bit microprocessor for a sequence control using a field programmable gate array(FPGA). The microprocessor was designed by a VHDL with top down method, the program memory was separated from the data memory for high speed execution of sequence instructions. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 32 bits. And the real time debug operation was implemented for easeful debugging the designed processor with a single step run, PC break point run, data memory break point run. Also in this designed microprocessor, pulse instructions, step controllers, master controllers, BM and BCD type arithmetic instructions, barrel shift instructions were implemented for sequence logic control. The FPGA was synthesized under a Xilinx's Foundation 4.2i Project Manager using a V600EHQ240 which contains 600,000 gates. Finally simulation and experiment were successfully performed respectively. For showing good performance, the designed microprocessor for the sequence logic control was compared with the H8S/2148 microprocessor which contained many bit instructions for sequence logic control. The designed processor for the sequence logic showed good performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.10B
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• pp.939-945
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• 2008

Tn this paper we described the process and the results of an implementation of Internet terminal using G.729.1 wideband speech codec for next generation network. For this purpose firstly we chose a high performance RISC application processor having DSP features for speech codec processing and enhanced Multimedia Accelerator(eMMA) function for video codec. In the implementation of this terminal, we used G.729.1 codec recently standardized in ITU-T which is a new scalable speech and audio codec that extends 0.729 speech coding standard. To adopt G.729.1 codec to this terminal we transformed most of the fixed point C codes which require more complexity into assembly codes so as to minimize processing time in the processor. As a result of this work we reduced the execution time of the original C codes about 80% and operated in real time on the terminal. For video we used H.263/MPEG-4 codec which is supported by the eMMA with hardware in the processor. In the SIP call processing test connected to real network we obtained under looms end-to-end delay and 3.8 MOS value measured with PESQ instrument. Besides this terminal operated well with commercial terminals.

• ETRI Journal
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• v.11 no.4
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• pp.105-118
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• 1989

HARP(High performance Architecture for RISC type Processor)는 고유의 명령어 세트, 데이터 타입, 메모리 입출력, 예외 처리 기능을갖는 32비트 VLSI 프로세서 구조이다. 마이크로 아키텍츄어는 설계된 구조를 기대할 수 있는최고 성능을 갖도록 구조(architecture)와 구현(implementation) 사이의 최적 모델링을 통해 정의되는 구조체로서 구조의 개념 설계를 구현의 실물 설계로 변환 시켜주는 조율(tuning)모델이다. HARP의 고유한 명령어 세트를 비롯한 구조적 기능들을 최적 구현 하기위해 32비트 크기의 명령어 입력 유니트(Instruction Fetch Unit), 데이터 입출력 유니트(Data I/O Unit), 명령어/데이터 처리유니트(Instruction/Data Processing Unit), 예외 상황 처리 유니트(Exception Processing Unit)등 4개 유니트가 설계되었으며 이들 4개 유니트의 동작을 최대 속도로 유지시키기 위해 각급 주요 설계 변수들이 시뮬레이션을 통해 최적화 되었다. 유효 채널길이 $0.7\mum$급 3층 메탈 배선의 HCMOS(High performance CMOS)공정 기술을 구현 기준 기술로 사용하여 50MHz외 동작 주파수에서 최대50 MIPS(Million Instructions Per Second)의 성능을 갖도록 3단계 파이프라인이 설계되었다. 단일 위상의 50MHz클럭 입력과 동기화된 명령어/데이터 입출력을 위해 액세스 타임 20nsec이내의 고속 메모리 입출력 구조가 시뮬레이션되었으며 설계된 마이크로 아키텍츄어를 이용하여 HARP구조의 기대된 최대 성능을 검증하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.990-994
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• 2003

This paper describes the VoIP(Voice over Internet Protocol) SoC(System on Chip) Design and the test board development for the function verification to support voice communication services using Internet. To implement the simple system of configuration, we designed the VoIP SoC which have ARM922T of 32bit microprocessor, IP network interface, voice signal interface, various user interface function. Also we developed test program and communication protocol to verify the function of this chip. We used several tools of design and simulation, developed and tested a test board with Excalibur which includes ARM922T microprocessor and FPGA.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.651-654
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• 2005

In this paper, we designed ECC(Elliptic Curve Cryptographic) Processor with Bus-splitting mothod for embedded SoC. ECC SIP is designed by VHDL RTL modeling, and implemented reusably through the procedure of logic synthesis, simulation and FPGA verification. To communicate with ARM9 core and SIP, we designed SIP bus functional model according to AMBA AHB specification. The design of ECC Processor for platform-based SoC is implemented using the design kit which is composed of many devices such as ARM9 RISC core, memory, UART, interrupt controller, FPGA and so on. We performed software design on the ARM9 core for SIP and peripherals control, memory address mapping and so on.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.473-476
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• 2001

본 논문에서는 32비트 MCU RISC 프로세서를 사용하여 MPEC 오디오 복호화기를 소프트웨어의 구현하였다. 구현된 MPEC 오디오 복호화기는 MPEC-2 Layer-III (MP3)와 MPEC-2 AAC 로 구성된다. 프로그래밍 가능한 소프트웨어로 구현하여 향후 성능 개선이나 새로운 기능을 추가할 수 있는 유연성을 극대화하였다. 복호화기 구현은 구현 시간과 비용을 고려하여 직접 어셈블리를 코딩하는 대신 최적화된 C 코드를 사용하여 컴파일하는 방법을 선택하였다. 이때 발생할 수 있는 성능 저하 요소들을 줄이기 위해 추가의 최적화 과정을 수행하여 성능을 개선하는 방법을 제시하였다. 구현된 복호화기의 출력 음질은 ISO 13818-4 compliance test 결과 Full compliance 를 만족하였다. 또한 연산량 최적화 결과 MP3 와 AAC 테스트 비트열에 대해 모두 35 MHz 이하의 동작 주파수로 동작이 가능함을 확인하였다.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.321-324
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• 2001

This paper describes a fast and low-power multiplier co-processor architecture for digital signal processing applications and real-time control systems and its use as a multiplier co-processor for a 32-bit RISC microprocessor utilizing its one of the 16 co-processor interfaces. Its architecture adopts various algorithms to reduce the dynamic power and the area as well. The designed multiplier performs 32$\times$32 bit multiplication, and was designed using verilog HDL and 0.35${\mu}{\textrm}{m}$, 3V, 4M CMOS standard cell library. Its target operating speed is 40MHz, area lower than 10000 gate counts, and 10mW/MHz of power.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.396-399
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• 1999

In this paper, the efficient HW/SW co-simulation method which selects the ISA model dynamically is proposed. Because the ISA models with only fixed accuracy have been used in previous co-simulation environment, it may result in bad performance in speed or accuracy. In the proposed method, the cycle accurate ISA model is used in the case that the states of the detailed system are to be inspected. In other case, instruction-based model is executed in order to accelerate the simulation speed. The proposed dynamic model selection can be done by setting the conversion point in the application code before the simulation starts. The experiment on the embedded RISC processor have been performed, and its result shows that the proposed method is more efficient than the case of using fixed ISA model.