• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.1-8
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• 2005

A $0.35\mu$m SiGe BiCMOS fabrication process has been timely developed, which is aiming at wireless RF ICs development and fast growing SiGe RF market. With non-selective SiGe epilayer, SiGe HBTs in this process used trapezoidal Ge base profile for the enhanced AC performance via Ge induced bandgap niuoin. The characteristics of hFE 100, $f_{T}\;45GHz,\;F_{max}\;50GHz,\;NF_{min}\;0.8dB$ have been obtained by optimizing not only SiGe base profile but also RTA condition after emitter polysilicon deposition, which enables the SiGe technology competition against the worldwide cutting edge SiGe BiCMOS technology. In addition, the process incorporates the CMOS logic, which is fully compatible with $0.35\mu$m pure logic technology. High Q passive elements are also provided for high precision analog circuit designs, and their quality factors of W(1pF) and inductor(2nH) are 80, 12.5, respectively.

• 한국ITS학회:학술대회논문집
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• 2008.11a
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• pp.607-610
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• 2008

• Proceedings of the IEEK Conference
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• 2004.06a
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• pp.221-224
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• 2004

This paper has researched on-chip spiral inductor in digital CMOS technology by modeling physical structure based on foundry parameter. To show the possibility of its application to RF design, we designed dual band RF front-end receiver. The simulated receiver have gain of 23/23.5 dB and noise figure of 2.8/3.36 dB at 2.45/5.25 GHz, respectively. It occupies $16mm^2$ in $0.25{\mu}m$ CMOS with 5 metal layer.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.675-681
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• 2016

A 41dB gain control range $6^{th}$-order band-pass receiver front-end (RFE) using CMOS switched frequency translated impedance (FTI) is presented in a 40 nm CMOS technology. The RFE consists of a frequency tunable RF band-pass filter (BPF), IQ gm cells, and IQ TIAs. The RF BPF has wide gain control range preserving constant filter Q and pass band flatness due to proposed pre-distortion scheme. Also, the RF filter using CMOS switches in FTI blocks shows low clock leakage to signal nodes, and results in low common mode noise and stable operation. The baseband IQ signals are generated by combining baseband Gm cells which receives 8-phase signal outputs down-converted at last stage of FTIs in the RF BPF. The measured results of the RFE show 36.4 dB gain and 6.3 dB NF at maximum gain mode. The pass-band IIP3 and out-band IIP3@20 MHz offset are -10 dBm and +12.6 dBm at maximum gain mode, and +14 dBm and +20.5 dBm at minimum gain mode, respectively. With a 1.2 V power supply, the current consumption of the overall RFE is 40 mA at 500 MHz carrier frequency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.11
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• pp.1228-1238
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• 2012

In this paper, we design, fabricate and measure two kinds of high-frequency packages for K-band CMOS FMCW radar chips using RF via structures. The packages are fabricated with the conventional PCB process and LTCC process. The design centering of the packages is performed at 24 GHz and impedance variation caused by the wire bonding and RF via structure is fully evaluated using 3D electromagnetic simulation. The RF via structure with characteristic impedance of $50{\Omega}$ is used to reduce impedance mismatch loss. Two kinds of test packages with back-to-back connected RF paths are fabricated and measured for the design verification of the PCB-based package and LTCC package. Their measured results show an insertion loss of less than 0.4 dB at 24 GHz and less than 0.5 dB for 20~29 GHz. The measured return loss is less than -13 dB for the PCB-based package and less than -15 dB for the LTCC package in the frequency band, but the return loss of the package itself is predicted to be better than that of the test package by about 5 dB, because the ripples of the back-to-back connection typically degrade the return loss by 5 dB or more.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.423-424
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• 2011

This paper has proposed a 920 MHz RF front-end for IEEE 802.15.4g SUN (Smart Utility Network) systems. The proposed 920 MHz RF front-end consists of a driver amplifier, a low noise amplifier, and a RF switch. In the TX mode, the driver amplifier has been designed as a single-ended topology to remove a transformer which causes a loss of the output power from the driver amplifier. In addition, a RF switch is located in the RX path not the TX path. In the RX mode, the proposed low noise amplifier can provide a differential output signal when a single-ended input signal has been applied to. A LC resonant circuit is used as both a load of the drive amplifier and a input matching circuit of the low noise amplifier, reducing the chip area. The proposed 920 MHz RF Front-end has been implemented in a 0.18-um CMOS technology. It consumes 3.6 mA in driver amplifier and 3.1 mA in low noise amplifier from a 1.8 V supply voltage.

• Information and Communications Magazine
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• v.21 no.6
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• pp.143-152
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• 2004

최근 RFID 국제 표준안이 확정되고 RFID 태그용 칩이 저가 생산이 가능하게 되면서 특히 물류 유통 분야를 중심으로 기존의 바코드를 대체하는 RFID 시스템의 상용화 가능성이 제시되고있다. 특히 감지거리가 길고 인식률이 좋은 UHF 대역의 기술적인 활용 가능성이 고조되면서 산업적으로 성공할 가능성이 더욱 커지고 있다. UHF 대역의 무선 태그의 생산 기술은 종래에는 GaAs 쇼트키 다이오드와 기타 RF회로를 CMOS 회로와 하나의 칩으로 통합하는 것이 어려워 저가, 초소형의 무선 태그용 칩을 실용화하지 못하였다 하지만 최근에 반도체 기술의 눈부신 발전과 CMOS RF 기술의 발전으로 RF 태그용 무선회로를 하나의 칩으로 통합하여 저가 생산으로 특히 유통 및 물류 분야를 중심으로 긍정적인 활용 결과 및 제품들이 등장하고 있다.(중략)

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.5 s.120
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• pp.530-538
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• 2007

An inductor library for efficient low cost RFIC design has been developed based on a standard digital 0.18 ${\mu}m$ CMOS process. The developed library provides four structural variations that are most popular in RFIC design; standard spiral structure, patterned ground shield(PGS) structure to enhance quality factor, stacked structure to enable high inductance values in a given silicon area, multilayer structure to lower series resistance. Electromagnetic simulation, equivalent circuit, and parameter extraction processes have been verified based on measurement results. The extensive measurement and simulation results of the inductor library can be a great asset for low cost RFIC design and development.

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.589-592
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• 2002

A CMOS power amplifier for IMT-2000 is designed with 0.25-${\mu}m$ CMOS technology. This amplifier circuits consist of two cascode stages. Used cascode structure has good reverse isolation. These amplifier circuits consist of two stages which are driver stage and power amplification stage. The designed power amplifier is simulated with ADS using 0.25-${\mu}m$ CMOS library at 3.3 V power supply. Simulation results indicate that the amplifier has a PAE of 39 % and power gain of 24 dBm at 1.95 GHz.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.1
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• pp.19-29
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• 2002

A simple and analytical design approach for input power matched CMOS RF LNA circuits and their scaling for lower power consumption, is introduced. In spite of the simplicity of our expressions, it gives excellent agreement with numerical simulation results using commercial CAD tools for several circuit examples performed at 2.4GHz using $0.18\mu\textrm{m}$ CMOS technology. These simple and analytical results are extremely useful in that they can provide enough insights not only for designing any CMOS LNA circuits, but also for characterizing and diagnosing them whether being prototyped or manufactured.