• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.17 no.2
• /
• pp.162-170
• /
• 2004

A 900MHz CMOS RF power amplifier with digitally controllable output power has been proposed and designed with 0.6${\mu}{\textrm}{m}$ standard CMOS technology. The designed power amplifier was composed of digitally controllable switch mode pre-amplifiers with an integrated 4nH spiral inductor load and class-C output stage. Especially, to compensate the 1ow Q of integrated spiral inductor, cascode amplifier with a Q-enhancement circuit is used. It has been shown that the proposed power control technique allows the output power to change from almost 3dBm to 13.5dBm. And it has a maximum PAE(Power Added Efficiency) of almost 55％ at 900MHz operating frequency and 3V power supply voltage.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.16 no.5
• /
• pp.1009-1014
• /
• 2012

This paper has proposed a 2,500 MHz ~ 2,570 MHz 0.13-${\mu}m$ CMOS RF front-end transmitter for LTE-Advanced systems. The proposed RF front-end transmitter is composed of a quadrature up-conversion mixer and a driver amplifier. The measurement results show the maximum output power level is +6 dBm and the suppression ratio for the image sideband and LO leakage are better than -40 dBc respectively. The fabricated chip consumes 36 mA from a 1.2 V supply voltage.

• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.795-798
• /
• 2003

In this paper, a CMOS Tx RF/IF single chip for PCS applications is designed. The chip consumes 84mA from a 3V supply and the layout area without pads is 1.6mm$\times$3.5mm. Simulation results show that the RF block composed of a SSB RF block and a driver amplifier exhibits a gain of 14.8dB and an OIP3 of 7dBm. The image and carrier suppressions are 35dBc and 31dBc, respectively. The designed circuits are under fabrication using a 0.35${\mu}{\textrm}{m}$ CMOS process.

• Journal of the Korean Institute of Telematics and Electronics S
• /
• v.35S no.9
• /
• pp.19-27
• /
• 1998

The Transmitter part of single RF transceiver chip for an extended GSM handset application was circuit-designed, fabricated adn evaluated. The RF-IC Chip was processed by 0.8${\mu}m$ Si BiCMOS, 80 pin TQFP of $10 {\times} 10mm$ size, 3.3V operated RF-IC reveals, in general, quite reasonable integrity and RF performances. This paper describes development resuts of RF transmitter section, which includes IF/RF up-conversion mixer, IF/RF polyphase and pre-amplifier. The test results show that RF transmitter section is well operated within frequency range of 880~915MHz, which is defined on the extended GSM(E-GSM) specification. The transmitter section also reveals moderate power consumption of 71mA and total output power of 8.2dBm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.21 no.4
• /
• pp.443-451
• /
• 2010

This paper describes a fully integrated CMOS low-IF mobile-TV RF tuner for Band-III T-DMB/DAB applications. All functional blocks such as low noise amplifier, mixers, variable gain amplifiers, channel filter, phase locked loop, voltage controlled oscillator and PLL loop filter are integrated. The gain of LNA can be controlled from -10 dB to +15 dB with 4-step resolutions. This provides a high signal-to-noise ratio and high linearity performance at a certain power level of RF input because LNA has a small gain variance. For further improving the linearity and noise performance we have proposed the RF VGA exploiting Schmoock's technique and the mixer with current bleeding, which injects directly the charges to the transconductance stage. The chip is fabricated in a 0.18 um mixed signal CMOS process. The measured gain range of the receiver is -25~+88 dB, the overall noise figure(NF) is 4.02~5.13 dB over the whole T-DMB band of 174~240 MHz, and the measured IIP3 is +2.3 dBm at low gain mode. The tuner rejects the image signal over maximum 63.4 dB. The power consumption is 54 mW at 1.8 V supply voltage. The chip area is $3.0{\times}2.5mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.3
• /
• pp.20-26
• /
• 2000

In this work, the degradation of g$_{m}$ , f$_{T}$ and f$_{max}$ of RF-CMOS devices have been characterized at elevated temperature. Since MOS transistors in RF applications are usually in saturation region, a simple empirical model for temperature dependence of g$_{m}$ at any measurement bias has been suggested. Because f$_{T}$ and f$_{max}$ of CMOS devices are proportional to g$_{m}$, the temperature dependence of f$_{T}$ and f$_{max}$ could be obtained from the temperature dependence of g$_{m}$. It was found that the degradation of f$_{T}$ and f$_{max}$ at elevated temperature was due to the degradation of g$_{m}$. From the correlation between DC and RF performances of CMOS devices, we can predict the enhanced f$_{T}$ and f$_{max}$ performances at low temperature.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.15 no.2
• /
• pp.273-278
• /
• 2011

This paper has proposed a dual-band transmitter RF Front-end for IMT-Advanced systems which has been implemented in a 0.13-${\mu}m$ CMOS technology. The proposed dual-band transmitter RF Front-End covers 2300~2700 MHz, 3300~3800 MHz frequency ranges which support 802.11, Mobile WiMAX, and IMT-Advanced system. The proposed dual-band transmitter RF Front-End consumes 45 mA from a 1.2 V supply voltage. The performances of the transmitter RF Front-End are verified through post-layout simulations. The simulation results show a +0 dBm output power at 2 GHz band, and +1.3 dBm output power at 3 GHz band.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.52 no.9
• /
• pp.21-27
• /
• 2015

An improved method based on direct extraction and simultaneous optimization is developed to determine model parameters of symmetric inductors fabricated by the high resistivity(HR) silicon-on-insulator(SOI) RF CMOS process. In order to improve modeling accuracy, several model parameters are directly extracted by Y and Z-parameter equations derived from two equivalent circuits of symmetric inductor and grounded center-tap one, and the number of unknown parameters is reduced using parallel resistance and total inductance equations. In order to improve optimization accuracy, two sets of measured S-parameters are simultaneously optimized while same model parameters in two equivalent circuits are set to common variables.

• Journal of IKEEE
• /
• v.4 no.2 s.7
• /
• pp.202-211
• /
• 2000

Utilizing the circuit simulator SPICE, we designed a 1.9GHz CMOS up-conversion mixer and explained in detail the simulation procedures including device modeling for the circuit design. Since the measured characteristics of the chip fabricated using the $0.5{\mu}m$ standard CMOS process had shown a big deviation from the characteristics expected by the original simulations, we tried to figure out the proper reasons for the discrepancies. Simulations considering the discovered problems in the original simulations have shown the validity of the simulation method tried for the design. We have shown that the utilized standard CMOS process can be used for the implementation of the chip characteristics similar to those of the equivalent chip fabricated using the GaAs MESFET process.

• Journal of Advanced Information Technology and Convergence
• /
• v.10 no.1
• /
• pp.37-43
• /
• 2020

This paper presents analysis of passive metal interconnection of the LNA block in CMOS integrated circuit. The performance of circuit is affected by the geometry of RF signal path. To investigate the effect of interconnection lines, a cascode LNA is designed, and circuit simulations with full-wave electromagnetic (EM) simulations are executed for different positions of a component. As the results, the position of an external capacitor (C_ex) changes the parasitic capacitance of electric coupling; the placement of component affects the circuit performance. This analysis of interconnection line is helpful to analyze the amount of electromagnetic coupling between the lines, and useful to choose the signal path in the layout design. The target of this work is the RF LNA enabling the seamless connection of wireless data network and the following standards have to be supported in multi-band (WCDMA: 2.11~ 2.17 GHz, CDMA200 1x : 1.84~1.87 GHz, WiBro : 2.3~2.4GHz) mobile application. This work has been simulated and verified by Cadence spectre RF tool and Ansoft HFSS. And also, this work has been implemented in a 0.13um RF CMOS technology process.