Journal of Advanced Information Technology and Convergence (한국정보기술학회 영문논문지)

Korean Institute of Information Technology (한국정보기술학회)
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Design and Analysis of 2 GHz Low Noise Amplifier Layout in 0.13um RF CMOS

  • Lee, Miyoung (Department of electrical and electronics engineering, Hannam University)
  • Received : 2020.07.07
  • Accepted : 2020.07.25
  • Published : 2020.07.31
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Abstract

This paper presents analysis of passive metal interconnection of the LNA block in CMOS integrated circuit. The performance of circuit is affected by the geometry of RF signal path. To investigate the effect of interconnection lines, a cascode LNA is designed, and circuit simulations with full-wave electromagnetic (EM) simulations are executed for different positions of a component. As the results, the position of an external capacitor (Cex) changes the parasitic capacitance of electric coupling; the placement of component affects the circuit performance. This analysis of interconnection line is helpful to analyze the amount of electromagnetic coupling between the lines, and useful to choose the signal path in the layout design. The target of this work is the RF LNA enabling the seamless connection of wireless data network and the following standards have to be supported in multi-band (WCDMA: 2.11~ 2.17 GHz, CDMA200 1x : 1.84~1.87 GHz, WiBro : 2.3~2.4GHz) mobile application. This work has been simulated and verified by Cadence spectre RF tool and Ansoft HFSS. And also, this work has been implemented in a 0.13um RF CMOS technology process.

Keywords

Acknowledgement

This paper has been supported by 2020 Hannam University Research Fund.

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