• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.399-402
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• 2004

This paper presents a system-on-chip prototype implementing a full integration for a portable digital audio system. The chip is composed of a audio processor block to implements audio decoding and voice compression or decompression software, a system control block including 8-bit MCU core and Memory Management Unit (MMU) a low power 16-bit ${\Sigma}{\Delta}$ CODEC, two DC-to-BC converter, and a flash memory controller. In order to support other audio algorithms except Mask ROM type's fixed codes, a novel 16-bit fixed-point DSP core with the program-download architecture is proposed. Funker, an efficient power management technique such as task-based clock management is implemented to reduce power consumption for portable application. The proposed chip has been fabricated with a 4 metal 0.25um CMOS technology and the chip area is about 7.1 mm ${\times}$ 7.1mm with 100mW power dissipation at 2.5V power supply.

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.131-135
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• 2000

본 논문에서는 고성능 고정 소수점 DSP (Digital Signal Processor) 코어인 Vincent6 코어 [1]를 이용하여 ITU-T C.728 음성 부호화기를 실시간으로 구현하였다 G.728 은 16 kb/s전송률의 ITU-T표준 음성 부호화기이며, 입력신호는 8 kHz로 샘플링되며 샘플 당 16 bit 로 양자화된 PCM 신호이다. G.728 은 LD-CELP(Low Delay Code Excited Linear Prediction)라고도 하며, 알고리 듬 delay는 0.625ms 이다. Vincent6 DSP core 는 VLIW (Very-Long Instruction Word) 특성을 가지므로 다중 명령 (multiple instruction)을 수행할 수 있다 이를 위해서 G.728 annex G를 이용하여 고정 소숫점 연산으로 코드를 작성한 후, 이를 vincent6 어셈블리 코드로 구현하였다. 최종적으로 구현된 코드는 ITU-T 의 test vector 에 대 해 bit exact 한 결과를 보이며 34 MCPS (Million Cycles Per Second)의 계산량을 가지며 사용 메모리크기는 데이터 메모리가 약 9KByte, 프로그램 메모리가 약 57 KByte 이다.

• Journal of Advanced Navigation Technology
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• v.14 no.1
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• pp.57-65
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• 2010

In this paper, we propose the structure of heterogeneous multiprocessor's concept, which is the structure of the new type of the robot controller, and we introduce an integrating structure method, which is distributed multiprocessor within controller using sRIO. We also perform the computer simulation with using the sRIO IP core which was designed within FPGA as the method for implementation of integrated heterogeneous multiprocessor by sRIO communication. Thus, we verify the result.

• Smart Media Journal
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• v.3 no.4
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• pp.9-15
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• 2014

A virtual platform models a processor core and the peripheral devices constituting the SoC in software. Major companies utilize a variety of platforms for product development with optimal SW+SoC integrated system architecture design and IP reuse based Top-Down design flow using a virtual platform. In this paper, we propose a virtual platform based on OpenRISC, an open source RISC based core. The proposed virtual platform supports high speed emulation of approximately 20 MIPS using DBT (Dynamic Binary Translation).

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.53 no.4
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• pp.214-220
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• 2004

This paper describes a busbar current differential relay in conjunction with a current transformer(CT) compensating algorithm irrespective of the level of the remanent flux. The compensating algorithm detects the start of first saturation if the third-difference function of the current exceeds the threshold; it estimates the core flux at the first saturation start by inserting the negative value of the third-difference function of the current into the magnetization curve; thereafter, it calculates the core flux during the fault and compensates the distorted current using the magnetization curve. The algorithm estimates the correct secondary current irrespective of the level of the remanent flux and needs no saturation point of the magnetization curve. The proposed relay can improve not only security of the relay on an external fault with CT saturation but sensitivity of the relay on an internal fault; the relay can improve the operating speed on n internal fault with CT saturation. This paper concludes by implementing the relay into a digital signal processor based prototype relay.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.53 no.4
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• pp.214-214
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• 2004

This paper describes a busbar current differential relay in conjunction with a current transformer(CT) compensating algorithm irrespective of the level of the remanent flux. The compensating algorithm detects the start of first saturation if the third-difference function of the current exceeds the threshold; it estimates the core flux at the first saturation start by inserting the negative value of the third-difference function of the current into the magnetization curve; thereafter, it calculates the core flux during the fault and compensates the distorted current using the magnetization curve. The algorithm estimates the correct secondary current irrespective of the level of the remanent flux and needs no saturation point of the magnetization curve. The proposed relay can improve not only security of the relay on an external fault with CT saturation but sensitivity of the relay on an internal fault; the relay can improve the operating speed on n internal fault with CT saturation. This paper concludes by implementing the relay into a digital signal processor based prototype relay.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.52 no.3
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• pp.158-164
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• 2003

This paper proposes a percentage current differential relaying algorithm for bus protection using an advanced compensating algorithm of the secondary current of current transformers (CTs). The compensating algorithm estimates the core flux at the start of the first saturation based on the value of the second-difference of the secondary current. Then, it calculates the core flux and compensates distorted currents using the magnetization curve. The algorithm Is unaffected by a remanent flux. The simulation results indicate that the proposed algorithm can discriminate internal faults from external faults when the CT saturates. This paper concludes by implementing the algorithm into a TMS320C6701 digital signal processor. The results of hardware implementation are also satisfactory. The proposed algorithm can improve not only stability of the relay in the case of an external fault but sensitivity of the relay in the case of an internal fault.

• IEMEK Journal of Embedded Systems and Applications
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• v.17 no.1
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• pp.59-65
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• 2022

Virtual memory is used as the method to ensure the safety of the system through memory protection in the real-time system. TLB miss caused by using virtual memory makes the real-time system WCET more pessimistically. TLB lockdown can be applied as a method to improve this problem. However, processors with limited TLB lockdown entries, a selection criterion is needed to efficiently utilize the TLB lockdown entry. In this paper, the most frequently accessed virtual pages in the process are applied to the TLB lockdown by analyzing memory profiling. The results showed that micro data TLB miss stall cycle and main data TLB miss stall cycle of the processor decreased by at least 4.7% and up to 29.7%.

• Journal of Satellite, Information and Communications
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• v.9 no.4
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• pp.73-76
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• 2014

With the increasing popularity of multi-core processors, they have been adopted even in embedded systems. Under this circumstance many multimedia applications can be parallelized on multi-core platforms because they usually require heavy computations and extensive memory accesses. This paper proposes an efficient thread-level parallel implementation for color space conversion on multi-core CPU. Thread-level parallelism has been becoming very useful parallel processing paradigm especially on shared memory computing systems. In this work, it is exploited by allocating different input pixels to each thread for concurrent loop executions. For the performance evaluation, this paper evaluate the performace improvements for color conversion on multi-core processors based on the processing speed comparison between its serial implementation and parallel ones. The results shows that thread-level parallel implementations show the overall similar ratios of performance improvements regardless of different multi-cores.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.2
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• pp.728-741
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• 2015

Stereo vision has become an important technical issue in the field of 3D imaging, machine vision, robotics, image analysis, and so on. The depth map extraction from stereo video is a key technology of stereoscopic 3D video requiring stereo correspondence algorithms. This is the matching process of the similarity measure for each disparity value, followed by an aggregation and optimization step. Since it requires a lot of computational power, there are significant speed-performance advantages when exploiting parallel processing available on processors. In this situation, multi-core CPU may allow many parallel programming technologies to be realized in users computing devices. This paper proposes parallel implementations for calculating disparity map using a shared memory programming and exploiting the streaming SIMD extension technology. By doing so, we can take advantage both of the hardware and software features of multi-core processor. For the performance evaluation, we implemented a parallel SAD algorithm with OpenMP and SSE2. Their processing speeds are compared with non parallel version on stereoscopic streaming video. The experimental results show that both technologies have a significant effect on the performance and achieve great improvements on processing speed.