• 한국IT서비스학회:학술대회논문집
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• 2009.05a
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• pp.205-208
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• 2009

이 논문에서는 RFID(Radio Frequency IDentification)에 대한 여러 가지 보안위협에 대하여 간단히 알아보고 그에 대응하는 안전한 암호학적 도구(Primitive)에 대하여 알아보겠다. 공개키 암호시스템(PKC, Public Key Cryptosystem)에 사용되는 타원곡선(EC, Elliptic Curve) 암호, NTRU(N-th degree TRUncated polynomial ring) 암호, Rabin 암호 등은 초경량 하드웨어 구현에 적합한 차세대 암호시스템으로서 안전한 RFID 인증서비스 제공과 프라이버시보호를 가능케 한다. 특히, 본고에서는 초경량 키의 길이, 저전력 소모성, 고속구현 속도를 갖는 타원곡선암호의 안전성에 대한 가이드라인을 제공하겠다.

• Journal of the Korea Society of Computer and Information
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• v.20 no.2
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• pp.1-10
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• 2015

In this paper, we propose a new multiplication algorithm for primitive polynomial with all 1 of coefficient in case that m is odd and even on finite fields $GF(3^m)$, and design the multiplier with parallel input-output module structure using the presented multiplication algorithm. The proposed multiplier is designed $(m+1)^2$ same basic cells. Since the basic cells have no a latch circuit, the multiplicative circuit is very simple and is short the delay time $T_A+T_X$ per cell unit. The proposed multiplier is easy to extend the circuit with large m having regularity and modularity by cell array, and is suitable to the implementation of VLSI circuit.

• Bulletin of the Korean Mathematical Society
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• v.59 no.6
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• pp.1511-1522
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• 2022

Let H be a subgroup of $\mathbb{Z}^*_n$ (the multiplicative group of integers modulo n) and h₁, h₂, …, h_l distinct representatives of the cosets of H in $\mathbb{Z}^*_n$. We now define a polynomial J_n,H(x) to be $$J_{n,H}(x)=\prod^l_{j=1} \left( x-\sum_{h{\in}H} {\zeta}^{h_jh}_n\right)$$, where ${\zeta}_n=e^{\frac{2{\pi}i}{n}}$ is the nth primitive root of unity. Polynomials of such form generalize the nth cyclotomic polynomial $\Phi_n(x)={\prod}_{k{\in}\mathbb{Z}^*_n}(x-{\zeta}^k_n)$ as J_n,{1}(x) = Φ_n(x). While the nth cyclotomic polynomial Φ_n(x) is irreducible over ℚ, J_n,H(x) is not necessarily irreducible. In this paper, we determine the subgroups H for which J_n,H(x) is irreducible over ℚ.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.4
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• pp.81-87
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• 1989

A cellular array multiplier for performing the multiplication of two elements in the finite field GF($2^m$) is presented in this paper. This multiplier is consisted of three operation part ; the multiplicative operation part, the modular operation part, and the primitive irreducible polynomial operation part. The multiplicative operation part and the modular operation part are composed by the basic cellular arrays designed AND gate and XOR gate. The primitive iirreducible operation part is constructed by XOR gates, D flip-flop circuits and a inverter. The multiplier presented here, is simple and regular for the wire routing and possesses the properties of concurrency and modularity. Also, it is expansible for the multiplication of two elements in the finite field increasing the degree m and suitable for VLSI implementation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.423-426
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• 2007

In this paper, we propose an algorithm for finding 90/150 Two Predecessor Nongroup Cellular Automata(TPNCA). Especially, we synthesize TPNCA for the minimal polynomial whose type is of the form xp(x) or x(x+1)p(x) using the proposed algorithm which is useful to study pseudorandom number generation, where p(x) is some primitive polynomial. Also we synthesize Two Predecessor Single Attractor CA and Two Predecessor Multiple Attractor CA which are useful to study hashing.

• Journal of information and communication convergence engineering
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• v.9 no.4
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• pp.435-440
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• 2011

This paper propose the method of constructing the highly efficiency adder and multiplier systems over finite fields. The addition arithmetic operation over finite field is simple comparatively because that addition arithmetic operation is analyzed by each digit modP summation independently. But in case of multiplication arithmetic operation, we generate maximum k=2m-2 degree of ${\alpha}^k$ terms, therefore we decrease k into m-1 degree using irreducible primitive polynomial. We propose two method of control signal generation for the purpose of performing above decrease process. One method is the combinational logic expression and the other method is universal signal generation. The proposed method of constructing the highly adder/multiplier systems is as following. First of all, we obtain algorithms for addition and multiplication arithmetic operation based on the mathematical properties over finite fields, next we construct basic cell of A-cell and M-cell using T-gate and modP cyclic gate. Finally we construct adder module and multiplier module over finite fields after synthesizing ${\alpha}^k$ generation module and control signal CSt generation module with A-cell and M-cell. Next, we constructing the arithmetic operation unit over finite fields. Then, we propose the future research and prospects.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.318-321
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• 2000

This paper propose the method of constructing the highly efficiency adder and multiplier systems over finite fie2, degree of uk terms, therefore we decrease k into m-1 degree using irreducible primitive polynomial. We propose two method of control signal generation for perform above decrease process. One method is the combinational logic expression and the other method is universal signal generation. The proposed method of constructing the highly adder/multiplier systems is as following. First of all, we obtain algorithms for addition and multiplication arithmetic operation based on the mathematical properties over finite fields, next we construct basic cell of A-cell and M-cell using T-gate and modP cyclic gate. Finally we construct adder module and multiplier module over finite fields after synthesize ${\alpha}$$\^$k/ generation module and control signal CSt generation module with A-cell and M-cell. Then, we propose the future research and prospects.

• ETRI Journal
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• v.30 no.4
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• pp.495-505
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• 2008

This paper presents a parallel processing searcher structure for the initial synchronization of a direct sequence ultra-wideband (DS-UWB) system, which is suitable for the digital implementation of baseband functionalities with a 1.32 Gsample/s chip rate analog-to-digital converter. An initial timing acquisition algorithm and a data demodulation method are also studied. The proposed searcher effectively acquires initial symbol and frame timing during the preamble transmission period. A hardware efficient receiver structure using 24 parallel digital correlators for binary phase-shift keying DS-UWB transmission is presented. The proposed correlator structure operating at 55 MHz is shared for correlation operations in a searcher, a channel estimator, and the demodulator of a RAKE receiver. We also present a pseudo-random noise sequence generated with a primitive polynomial, $1+x^2+x^5$, for packet detection, automatic gain control, and initial timing acquisition. Simulation results show that the performance of the proposed parallel processing searcher employing the presented pseudo-random noise sequence outperforms that employing a preamble sequence in the IEEE 802.15.3a DS-UWB proposal.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.856-859
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• 2005

This paper presents a method of constructing the highly efficiency arithmetic operation unit systems(AOUS) based on fields. The proposed AOUS is more regularity and extensibility than previous methods. Also, the proposed AOUS be able to apply basic multimedia hardware. The future research is demanded to more compact and advanced arithmetic operation algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.3
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• pp.510-520
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• 2011

In this paper, we propose a new multiplication algorithm for primitive polynomial with all 1 of coefficient in case that m is odd and even on finite fields $GF(3^m)$, and compose the multiplier with parallel input-output module structure using the presented multiplication algorithm. The proposed multiplier is designed $(m+1)^2$ same basic cells that have a mod(3) addition gate and a mod(3) multiplication gate. Since the basic cells have no a latch circuit, the multiplicative circuit is very simple and is short the delay time $T_A+T_X$ per cell unit. The proposed multiplier is easy to extend the circuit with large m having regularity and modularity by cell array, and is suitable to the implementation of VLSI circuit.