• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1436-1439
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• 2005

A novel current-type data driver for active matrix organic light emitting diode (AMOLED) is proposed for current uniformity enhancement among its output channels. New architecture is composed of shadow DACs that precharge output stages, a single-real DAC that correct the output level to a real target current level and output stages that operate in 3 states of sampling, correcting and driving. Simulation results show that the proposed driving method and circuits improve the current uniformity among output channels of a current-type driver IC.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.815-818
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• 2003

New sensing and writing schemes for a magneto-resistive random access memory (MRAM) with a twin cell structure are proposed. In order to enhance the cell reliability, a scheme of the low voltage precharge is employed to keep the magneto resistance (MR) ratio constant. Moreover, a common gate amplifier is utilized to provide sufficient voltage signal to the bit line sense amplifiers under the small MR ratio structures. To enhance the writing reliability, a current mode technique with tri-state current drivers is adopted. During write operations, the bit and /bit lines are connected. And 'HIGH' or 'LOW' data is determined in terms of the current direction flowing through the MTJ cell. With the viewpoint of the improved reliability of the cell behavior and sensing margin, HSPICE simulations proved the validity of the proposed schemes.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.6
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• pp.901-909
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• 1990

With a wide spread of 32 bit personal computers, a simple structure and high performance memory system have been highly required. In this paper, a memory block is constructed by using a modified hierarchical bit line in which the DRAM bit line and the latch which works as a SRAM cell are integrated by an interface gate. And the new architecture memory DSRAM(Dynamic Static RAM) is proposed by interleaving the 16 memory block. Because the DSRAM works with 16 page, the page is miss ratio becomes small and the RAS precharge time which is incurred by page miss is shortened. So the DSRAM can implement an optimum page interleaving and it has good compatibility to the existing DRAMs. The DSRAM can be widely used in small computers as well as a high performance memory system.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.7
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• pp.37-45
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• 1998

A 32-b self-timed parallel carry look-ahead adder (PCLA) designed for 0.5.mum. single threshold low power CMOS technology is demonstrated to operate with 2.7nsec delay at 8mW under 1V power supply. Compared to static PCLA and DPL adder, the self-timed PCLA designed with NORA logic provides the best performance at the power consumption comparable to other adder structures. The wave pipelined clock control play a crucial role in achieving the low power, high performance of this adder by eliminating the unnecessary power consumption due to the short-circuit current during the precharge phase. Th enoise margin has been improved by adopting the physical design of staic CMOS logic structure with controlled transistor sizes.

• Journal of the Korean Society of Industry Convergence
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• v.7 no.1
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• pp.115-120
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• 2004

An indoor air cleaner consisting of a dielectric barrier discharge system and an electrostatic precipitator (ESP) was experimentally investigated. The function of the dielectric barrier discharge is to precharge particles by producing nonthermal plasma before indoor air enters ESP, leading to an enhancement in dust collection efficiency. The dependence of particle size distribution on the plasma discharge was examined to understand the mechanism of the particle precharging. The plasma discharge was found to increase the electrical force of the particles, rather than agglomerate them. Coarse particles in the range of 0.5 to $5.0{\mu}m$ were observed to be easily collected by this indoor air cleaner, and the present study laid emphasis on the removal of fine particles of $0.3{\mu}m$. The collection efficiency of the fine particles was largely enhanced by the plasma discharge.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.3097-3099
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• 2000

In this paper, we design PLL for a low jitter and fast locking time that is used a new simple precharged CMOS phase frequency detector(PFD). The proposed PFD has a simple structure with using only 18 transistors. Futhermore, the PFD has a dead zone 25ps in the phase characteristic which is important in low jitter applications. The phase and frequency error detection range is not limited as the case of other precharge type PFDs. the simulation results base on a third order PLL are presented to verify the lock in process with the proposed PFD. the PLL using the new PED is designed using 0.25${\mu}m$ CMOS technology with 2.5V supply voltage.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.3
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• pp.401-417
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• 1994

In this paper, a new testable design technique for domino CMOS circuits is proposed to detect stuck-at(s-at), stuck-open(s-op) and stuck-on(s-on) faults in the circuits by observing logic test reponses. The proposed technique adds one pMOS transistor per domino CMOS gate for s-op and s-on faults testing of nMOS transistors and one nMOS transistors and one nMOS transistor per domino gate or multilevel circuit to detect s-on faults in pMOS transistors of inverters in the circuit. The extra transistors enable the proposed testable circuit to operate like a pseudo static nMOS circuit while testing nMOS transistors in domino CMOS circuits. Therefore, the two=phase operation of a precharge phase and a evaluation phase is not needed to keep the domino CMOS circuit from malfunctionong due to circuit delays in the test mode, which reduces the testing time and the complexity of test generation. Most faults of th transistors in the proposed testable domino CMOS circuit can be detected by single test patterns. The use of single test patterns makes the testing of the proposed testable domino CMOS circuit free from path delays, timing skews, chage sharing and glitches. In the proposed design, the testing of the faults which, require test sequences also becomes free from test invalidation. The conventional automatic test pattern generators(ATPG) can be used for generating test patterns to detect faults in the circuits.

• Korean Journal of Air-Conditioning and Refrigeration Engineering
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• v.15 no.9
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• pp.733-737
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• 2003

The purpose of this study is to analyze the particle removal characteristics of a commercial air cleaner based on the electrostatic precipitator. The air cleaner consists of a positive corona precharger to precharge particles and a collector to remove the charged particles. The test for particle removal efficiency is conducted with tobacco smoke particles of 1.27${\mu}{\textrm}{m}$ in mass median diameter. The result of one-pass filtration test shows that the filtration efficiency is more than 90% for the particles larger than 2.5 Um, while the efficiency for the particles of 0.5～1.0${\mu}{\textrm}{m}$ in case of 4.18 CMM is 70%. For the test room of 5,800${\times}$3,400${\times}$2,600㎣, the concentration of tobacco smoke particles decreases up to 30% of initial values within 30 minutes due to natural reduction and up to 90% of initial values within 30 minutes with the air cleaner operation.

• Journal of Korean Society for Atmospheric Environment
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• v.17 no.E2
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• pp.53-59
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• 2001

A hybrid dust-collector combining electrostatic charging with fabric filtration method was developed, and its performance characteristics were evaluated in this study. Charged particles build porous dendritic structure on the surfaces of filter by electrostatic attraction, increasing the collection efficiency of dust particles and reducing the pressure drop through the deposited dust layer and filter media. The cleaning performance of the dust layer is improved because the dendritic structured dust layer can be removed more easily by pulse jet cleaning flow. The results of the experiment showed a reduction of fine particle emission of 37% and the energy saving of 13% by precharging dust particles before filtration.

• ETRI Journal
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• v.37 no.6
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• pp.1188-1198
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• 2015

In this paper, a multi-time programmable (MTP) cell based on a $0.18{\mu}m$ bipolar-CMOS-DMOS backbone process that can be written into by using dual pumping voltages - VPP (boosted voltage) and VNN (negative voltage) - is used to design MTP memories without high voltage devices. The used MTP cell consists of a control gate (CG) capacitor, a TG_SENSE transistor, and a select transistor. To reduce the MTP cell size, the tunnel gate (TG) oxide and sense transistor are merged into a single TG_SENSE transistor; only two p-wells are used - one for the TG_SENSE and sense transistors and the other for the CG capacitor; moreover, only one deep n-well is used for the 256-bit MTP cell array. In addition, a three-stage voltage level translator, a VNN charge pump, and a VNN precharge circuit are newly proposed to secure the reliability of 5 V devices. Also, a dual memory structure, which is separated into a designer memory area of $1row{\times}64columns$ and a user memory area of $3rows{\times}64columns$, is newly proposed in this paper.