• 전기의세계
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• v.27 no.4
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• pp.45-51
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• 1978

A new method of realizing the field effect transistor with a sub-.mu. channel width is described. The sub-.mu. channel width is made possible by etching grooves into n$^{+}$ pn$^{[-10]}$ n$^{[-10]}$ structure and using p region at the wall for the channel region of the Metal-Oxide-Semiconductor transistor (MOST), or by diffusing two different types of impurities through the same diffusion mask and using p region at the surface for the channel region of MOST. When the drain voltage is increased at the pn$^{[-10]}$ drainjunction the depletion layer extends into the n$^{[-10]}$ region instead of into p region; this is also the secret of success to realize the sub-.mu. channel width. As the result of the experimental fabrication, a microwave MOST was obtained. The cut-off frequency was calculated to be 15.4 GHz by Linvill's power equation using the measured capacitances and transconductance.

• 한국신재생에너지학회:학술대회논문집
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• 2008.05a
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• pp.546-549
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• 2008

Hyundai Motor Company has made an effort to develop fuel cell electric vehicle and its subsystem in recent years. This paper deal with the development of electric drive system applied to Hyundai's fuel cell electric vehicle. This system is composed of three main components such as motor, inverter and DC/DC converter. The specifications of each system is introduced briefly and experimental result of its main components is presented. In addition, we introduce the development status of power semiconductor device, film capacitor, inductor and permanent magnet.

• Proceedings of the KIEE Conference
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• 1992.07b
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• pp.1063-1066
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• 1992

As the adjustable speed drives by means of PWM inverter are applied to a wider field of industries, the demands for lower acoustic noise caused by modulation is becoming more intense. With the development of high speed power semiconductor device such as the IGBTs, a higher carrier frequency can be adopted to increase the switching frequency to the supersonic range. The optimal magnitude of this signal is determined so that the sideband components near the carrier frequency are minimized

• Proceedings of the KIPE Conference
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• 2004.07b
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• pp.878-882
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• 2004

Position controls are very important in semiconductor manufacturing devices, machine tools precision measuring instruments, etc. In this paper, a novel encoder of digital and analog hybrid type is proposed. It is shown that from this experiment a high-resolution angle measurement device can be designed by a low cost incremental encoder.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.207-207
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• 2006

We investigated the effects of hydrogen addition to the growth process of SiC single crystal using sublimation physical vapor transport(PVT) techniques. Hydrogen was periodically added to an inert gas for the growth ambient during the SiC bulk growth Grown 2"-SiC single crystals were proven to be the polytype of 6H-SiC and carrier concentration levels of about $10^{17}/cm^3$ was determined from Hall measurements. As compared to the characteristics of SiC crystal grown without using hydrogen addition, the SiC crystal without definitely exhibited lower carrier concentration and lower microplpe density as well as reduced growth rate.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.281-283
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• 2005

Processing Plasmas are very sensitive to a variation in process parameters, To maintain process quality and device field, plasma malfunction should be tightly monitored with high sensitivity. A new monitoring method is presented and this was accomplished by applying discrete wavelet transformation to X-ray photoelectron spectroscopy. XPS data were collected during a plasma etching of silicon carbide. Various effects of DWT factor on fault sensitivity were optimized experimentally. Compared to raw data, total percent sensitivity for DWT data demonstrated a significantly improved sensitivity to plasma faults induced by bias power.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.32-39
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• 2008

Tunnel oxide of non-volatile memory (NVM) devices would be very difficult to downscale if ten-year data retention were still needed. This requirement limits further improvement of device performance in terms of programming speed and operating voltages. Consequently, for low-power applications with Fowler-Nordheim programming such as NAND, program and erase voltages are essentially sustained at unacceptably high levels. A promising solution for tunnel oxide scaling is tunnel barrier engineering (TBE), which uses multiple dielectric stacks to enhance field-sensitivity. This allows for shorter writing/erasing times and/or lower operating voltages than single $SiO_2$ tunnel oxide without altering the ten-year data retention constraint. In this paper, two approaches for tunnel barrier engineering are compared: the crested barrier and variable oxide thickness. Key results of TBE and its applications for NVM are also addressed.

• Journal of Institute of Control, Robotics and Systems
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• v.10 no.4
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• pp.371-376
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• 2004

Distributed Network Protocol Version 3.0 (DNP3.0) is the communication protocol developed for the interoperability between a RTU and a central control station of SCADA in the power utility industry. In this paper DNP3.0 is implemented by using HDL with FPGA and C program on Hitachi H8/532 processor. DNP3.0 is implemented from physical layer to network layer in hardware level to reduce the computing load on a CPU. Finally, the ASIC for DNP3.0 has been manufactured from Hynix Semiconductor. The commercial feasibility of the hardware through the communication test with ASE2000 and DNP Master Simulator is performed. The developed protocol becomes one of IP, and can be used to implement SoC for the terminal device in SCADA systems. Also, the result can be applicable to various industrial controllers because it is implemented in HDL.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.04a
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• pp.921-926
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• 1997

SOI(Silicon On lnsulator) technology is many advantages in the gabrication of MOS(Metal-Oxide Semiconductor) and CMOS(Complementary MOS) structures. These include high speed, lower dynamic power consumption,greater packing density, increased radiation tolearence et al. In smiple form of bonded SOL wafer manufacturing, creation of a bonded SOI structure involves oxidizing at least one of the mirror polished silicon surfaces, cleaning the oxidized surface and the surface of the layer to which it will be bonded,bringing the two cleanded surfaces together in close physical proximity, allowing the subsequent room temperature bonding to proceed to completion, and than following this room temperature joining with some form of heat treatment step,and device wafer is thinned to the target thickness. This paper has been performed to investigate the possibility of the bonded SOI wafer manufacturing Especially, we focused on the bonding quality and thinning method. Finally,we achieved the bonded SOI wafer that Si layer thickness is below 3 .mu. m and average roughness is below 5.angs.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.2
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• pp.110-116
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• 2009

The prominent advantages of Dual Material Surrounding Gate (DMSG) MOSFETs are higher speed, higher current drive, lower power consumption, enhanced short channel immunity and increased packing density, thus promising new opportunities for scaling and advanced design. In this Paper, we present Transconductance-to-drain current ratio and electric field distribution model for dual material surrounding gate (DMSGTs) MOSFETs. Transconductance-to-drain current ratio is a better criterion to access the performance of a device than the transconductance. This proposed model offers the basic designing guidance for dual material surrounding gate MOSFETs.