• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.5
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• pp.270-275
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• 2017

Current progress in the development of semiconductor technology in applications involving high electron mobility transistors (HEMT) and power devices is hindered by the lack of adequate ways todissipate heat generated during device operation. Concurrently, electronic devices that use gallium nitride (GaN) substrates do not perform well, because of the poor heat dissipation of the substrate. Suggested alternatives for overcoming these limitations include integration of high thermal conductivity material like diamond near the active device areas. This study will address a critical development in the art of GaN on diamond (GOD) structure by designing for ideal heat dissipation, in order to create apathway with the least thermal resistance and to improve the overall ease of integrating diamond heat spreaders into future electronic devices. This research has been carried out by means of heat transfer simulation, which has been successfully demonstrated by a finite-element method.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.4
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• pp.295-301
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• 2008

Recently, the demand on mm-wave (millimeter-wave) applications has increased dramatically. While circuits operating in the mm-wave frequency band have been traditionally implemented in III-V or SiGe technologies, recent advances in Si MOSFET operation speed enabled mm-wave circuits realized in a Si CMOS technology. In this work, a 58 GHz CMOS LC cross-coupled VCO (Voltage Controlled Oscillator) was fabricated in a $0.13-{\mu}m$ Si RF CMOS technology. In the course of the circuit design, active device models were modified for improved accuracy in the mm-wave range and EM (electromagnetic) simulation was heavily employed for passive device performance predicttion and interconnection parasitic extraction. The measured operating frequency ranged from 56.5 to 58.5 GHz with a tuning voltage swept from 0 to 2.3 V. The minimum phase noise of -96 dBc/Hz at 5 MHz offset was achieved. The output power varied around -20 dBm over the measured tuning range. The circuit drew current (including buffer current) of 10 mA from 1.5 V supply voltage. The FOM (Figure-Of-Merit) was estimated to be -165.5 dBc/Hz.

• 한국전산유체공학회:학술대회논문집
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• 2011.05a
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• pp.117-123
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• 2011

The low electric power and high efficiency chips are required because of the appearance of smart phones. Also, high-capacity memory chips are needed. e-MMC(embedded Multi-Media Card) for this is defined by JEDEC(Joint Electron Device Engineering Council). The e-MMC memory for research and development is a memory mulit-chip module of 64GB using 16-multilayers of 4GB NAND-flash memory. And it has simplified the chip by using SIP technique. But mulit-chip module generates high heat by higher integration. According to the result of study, whenever semiconductor chip is about 10 $^{\circ}C$ higher than the design temperature it makes the life of the chip shorten more than 50%. Therefore, it is required that we solve the problem of heating value and make the efficiency of e-MMC improved. In this study, geometry of 16-multilayered structure is compared the temperature distribution of four different geometries along the numerical analysis. As a result, it is con finned that a multilayer structure of stair type is more efficient than a multilayer structure of vertical type because a multi-layer structure of stair type is about 9 $^{\circ}C$ lower than a multilayer structure of vertical type.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.1
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• pp.103-108
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• 2002

The metal-oxide-semiconductor field-effect transistor(MOSFET) has undergone many changes in the last decade In response to the constant demand for increased speed, decreased power, and increased packing density. The state -of-the-art simulation programs are developed by engineers and scientists. This paper has compared commercial programs of Micro-tec and ISE-TCAD in device simulation. This paper investigates LDD MOSFET using two simulators. Bias condition is applied to the devices with gate lengths(Lg) 180㎚. We have presented MOSFET's characteristics such as I-V characteristic and electric field, and compared Micro-tec with ISE TCAD.

• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.1247-1249
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• 1993

In this paper, NUDFET(NonUniformly Doped Field Effect Transistor) is presented as an alternative which offers the possibility of reducing the power necessary to operate switching circuits without a substantial loss in speed. The purpose of this NUDFET is to modify the electric field profile in order to cause carrier velocity saturation to occur at a lower voltage than it would occur in the uniformly doped device of the same channel length. The more MESFET and NUDFET circuits are realized, the more accurate model ins the performance of these devices become required. Analytic model ins was replaced by numerical analysis because of the complexity of device configuration. In this paper, FEM is selected because of simpler local mesh refinement and smaller computer memory than FDM. For accurate analysis, this paper has applied the Scharfetter-Gummel(S-G) Scheme and seven-point Gaussian Quadrature rule to assembly of the finite-element stiffness matrices and right-hand side vector of the semiconductor equations.

• Journal of the Korea Safety Management & Science
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• v.17 no.3
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• pp.355-362
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• 2015

There has been an increase of using Bosch Process to fabricate MEMS Device, TSV, Power chip for straight etching profile. Essentially, the interest of TSV technology is rapidly floated, accordingly the demand of Bosch Process is able to hold the prominent position for straight etching of Si or another wafers. Recently, the process to prevent under etching or over etching using EPD equipment is widely used for improvement of mechanical, electrical properties of devices. As an EPD device, the OES is widely used to find accurate end point of etching. However, it is difficult to maintain the light source from view port of chamber because of contamination caused by ion conflict and byproducts in the chamber. In this study, we adapted the SPOES to avoid lose of signal and detect less open ratio under 1 %. We use 12inch Si wafer and execute the through etching 500um of thickness. Furthermore, to get the clear EPD data, we developed an algorithm to only receive the etching part without deposition part. The results showed possible to find End Point of under 1 % of open ratio etching process.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.263-267
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• 2014

Super junction trench gate power MOSFETs have been receiving attention in terms of the trade-off between breakdown voltage and on-resistance. The vertical structure of super junction trench gate power MOSFETs allows the on-resistance to be reduced compared with conventional Trench Gate Power MOSFETs. The heat release of devices is also decreased with the reduction of on-resistance. In this paper, Lattice Temperature of two devices, Trench Gate Power MOSFET and Super junction trench gate power MOSFET, are compared in several temperature circumstance with the same Breakdown Voltage and Cell-pitch. The devices were designed by 100V Breakdown voltage and measured from 250K Lattice Temperature. We have tried to investigate how much temperature rise in the same condition. According as temperature gap between top of devices and bottom of devices, Super junction trench gate power MOSFET has a tendency to generate lower heat release than Trench Gate Power MOSFET. This means that Super junction trench gate power MOSFET is superior for wide-temperature range operation. When trench etching process is applied for making P-pillar region, trench angle factor is also important component. Depending on trench angle, characteristics of Super junction device are changed. In this paper, we focus temperature characteristic as changing trench angle factor. Consequently, Trench angle factor don't have a great effect on temperature change.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.3
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• pp.21-30
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• 2018

Driven by the recent energy saving trend, conventional silicon based power conversion modules are being replaced by modules using silicon carbide. Previous papers have focused mainly on the electrical advantages of silicon carbide semiconductors that can be used to design switching devices with much lower losses than conventional silicon based devices. However, no systematic study of their thermomechanical reliability in power conversion modules using finite element method (FEM) simulation has been presented. In this paper, silicon and silicon carbide based power devices with three-phase switching were designed and compared from the viewpoint of thermomechanical reliability. The switching loss of power conversion module was measured by the switching loss evaluation system and measured switching loss data was used for the thermal FEM simulation. Temperature and stress/strain distributions were analyzed. Finally, a thermal fatigue simulation was conducted to analyze the creep phenomenon of the joining materials. It was shown that at the working frequency of 20 kHz, the maximum temperature and stress of the power conversion module with SiC chips were reduced by 56% and 47%, respectively, compared with Si chips. In addition, the creep equivalent strain of joining material in SiC chip was reduced by 53% after thermal cycle, compared with the joining material in Si chip.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.62-62
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• 2015

In this study, we study the effects of CF4 plasma treatment on the characteristics of enhancement mode (E-mode) AlGaN/GaN high electron mobility transistors (HEMTs). The CF4 plasma is generated by inductively coupled plasma reactive ion etching (ICP-RIE) system. The CF4 gas is decomposed into fluorine ions by ICP-RIE and then fluorine ions will effect the AlGaN/GaN interface to inhibit the electron transport of two dimension electron gas (2DEG) and increase channel resistance. The CF4 plasma method neither like the recessed type which have to utilize Cl2/BCl3 to etch semiconductor layer nor ion implantation needed high power to implant ions into semiconductor. Both of techniques will cause semiconductor damage. In the experiment, the CF4 treatment time are 0, 50, 100, 150, 200 and 250 seconds. It was found that the devices treated 100 seconds showed best electric performance. In order to prove fluorine ions existing and CF4 plasma treatment not etch epitaxial layer, the secondary ion mass spectrometer confirmed fluorine ions truly existing in the sample which treatment time 100 seconds. Moreover, transmission electron microscopy showed that the sample treated time 100 seconds did not have etch phenomena. Atomic layer deposition is used to grow Al2O3 with thickness 10, 20, 30 and 40 nm. In electrical measurement, the device that deposited 20-nm-thickness Al2O3 showed excellent current ability, the forward saturation current of 210 mA/mm, transconductance (gm) of 44.1 mS/mm and threshold voltage of 2.28 V, ION/IOFF reach to 108. As IV concerning the breakdown voltage measurement, all kinds of samples can reach to 1450 V.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.91-97
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• 2013

In this paper, a current steering 10-bit CMOS D/A converter to drive a NTSC/PAL analog TV is proposed. The proposed D/A converter has a 50MS/s operating speed with a 6+4 segmented type. Further, in order to minimize the device mismatch, a self-calibration bias technique with a fully integrated termination resistance is discussed. The chip has been fabricated with a 3.3V 0.11um 1-poly 6-metal CMOS technology. The effective chip area is $0.35mm^2$ and power consumption is about 88mW. The experimental result of SFDR is 63.1dB, when the input frequency is 1MHz at the 50MHz of sampling frequency.