• 제목/요약/키워드: Power reduction technique

검색결과 464건 처리시간 0.042초

EMC Compatability Analysis on Geostationary Satellite (정지궤도 인공위성의 전자파 호환성 해석)

  • Chae, Tae-Byeong;Oh, Seung-Hyeub
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • 제36권12호
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    • pp.1207-1215
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    • 2008
  • Satellite generates a complex electromagnetic noise by conducted and radiated coupling effect of the various electrical instruments. This noise may cause serious problems on the satellite system. To minimize the electromagnetic coupling effects and maintain the system safety margin, system noise reduction technique should be applied from the beginning of the system design. The COMS system is evaluated by measuring the conducted noise on system electrical power leads at PSR(Power Supply Regulator) and verifying a 6 dB system safety margin under the complex noise environment with current injection. The radiated noise due to the complex transmit antenna configuration is evaluated by integrating all unit-level RE measurement results, and the RF compatibility between spacecraft and launch vehicle is analyzed with the above estimations. This paper describes the COMS EMC compatibility analysis with respect to each unit level EMC test results, and RF compatibility analysis between spacecraft and launch vehicle. The analyzed results will be reflected on FM(Flight Model) EMC test.

Performance Evaluation of Convolution Coding OFDM Systems (컨볼루션 코딩 OFDM 시스템의 성능 분석)

  • Choi, Seung-Kuk
    • Journal of the Korea Institute of Information and Communication Engineering
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    • 제17권2호
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    • pp.294-301
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    • 2013
  • OFDM technique uses multiple sub-carriers for the data transmission. Therefore, bit error rate increases because of inter-carrier interference caused by nonlinear high power amplifier and carrier frequency offset. Wireless OFDM transmission over multi path fading channels is characterized by small transmission gain in multiple sub-carrier frequency interval. Therefore bit error rate increases because of burst errors. Inter-leaver and convolution error control coding are effective for the reduction of this burst error. Pilot symbol is used for the channel estimation in OFDM systems. However, imperfect channel estimates in this systems degrade the performance. The performance of this convolution coding OFDM systems using inter-leaver, gauged by the bit error rate, is analyzed considering the nonlinear high power amplifier, carrier frequency offset and channel estimation error.

A New High-Efficiency CMOS Darlington-Pair Type Bridge Rectifier for Driving RFID Tag Chips (RFID 태그 칩 구동을 위한 새로운 고효율 CMOS 달링턴쌍형 브리지 정류기)

  • Park, Kwang-Min
    • Journal of the Korea Academia-Industrial cooperation Society
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    • 제13권4호
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    • pp.1789-1796
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    • 2012
  • In this paper, a new high-efficiency CMOS bridge rectifier for driving RFID tag chips is designed and analyzed. The input stage of the proposed rectifier is designed as a cascade structure connected with two NMOSs for reducing the gate capacitance by circuitry method, which is the main path of the leakage current that is increased when the operating frequency is increased. This gate capacitance reduction technique using the cascade input stage for reducing the gate leakage current is presented theoretically. The output characteristics of the proposed rectifier are derived analytically using its high frequency small-signal equivalent circuit. For the general load resistance of $50K{\Omega}$, the proposed rectifier shows better power conversion efficiencies of 28.9% for 915MHz UHF (for ISO 18000 -6) and 15.3% for 2.45GHz microwave (for ISO 18000-4) than those of 26.3% and 26.8% for 915MHz, and 13.2% and 12.6% for 2.45GHz of compared other two existing rectifiers. Therefore, the proposed rectifier may be used as a general purpose rectifier to drive tag chips for various RFID systems.

Application of Concurrent Engineering for Conceptual design of a Future Main Battle Tank (차세대 주력전차의 개념설계를 위한 동시공학의 적용)

  • 김진우;소한균
    • Journal of the Korea Institute of Military Science and Technology
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    • 제2권1호
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    • pp.38-60
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    • 1999
  • The main objective of this study is systemization of the technique of ROC quantification and optimization of baseline design by applying CE principle to the acquisition process of a weapon system. QFD and TOA techniques can be employed to a good working example of the conceptual design of a future main battle tank. In this paper, Product Planning Phase, the first phase of four QFD phases, is deployed in terms of eight steps including customer requirements and final product control characteristics. TOA is carried out considering only combat weight. In order to perform combat weight analysis and performance TOA, Preliminary Configuration Synthesis Methodology is used. Preliminary Configuration Synthesis Methodology employs the method of least squares and described linear equations of weight interrelation equation for each component of tank. As a result of QFD based upon the ROC, it was cleared that armor piercing power, main armament, type of ammunition, cruising range, combat weight, armor protection, power loading, threat detection and cost are primary factors influencing design and that combat weight is the most dominant one. The results of TOA based on the combat weight constraint show that 5100 lb reduction was required to satisfy the ROC. The baseline design of a future main battle tank is illustrated with assumption that all phases of QFD are employed to development and production process of subsystems, components, and parts of main battle tank. TOA is applied in iterative process between initial baseline design and ROC. The detailed design of each component is illustrated for a future main battle tank.

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Charge Copy Method for Reduction of Cross Regulation in SIDO Boost Converter (SIDO boost converter에서 크로스 레귤레이션을 줄이기 위한 전하 복사방법)

  • Hwang, Wonjune;Kim, Ju Eon;Baek, Kwang-Hyun
    • Journal of IKEEE
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    • 제20권4호
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    • pp.432-434
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    • 2016
  • In conventional SIDO(Single Inductor Dual Output) boost converter, charging time is changed by load power consumption. In this case, if the power consumption of one load is changed to such a degree that switching frequency of the boost converter must be changed, another load charge time is also changed, which this causes cross regulation. In this paper, the charge copy technique is proposed to reduce cross regulation. When the switching frequency is changed to an integer ratio, another load charge time is also changed to integer ratio. Simulation result shows that proposed method reduces the 10.24mV cross regulation and 39.118us recover-time compared with conventional method.

A Design of Full-wave Rectifier for Measurement Instrument (계측기용 새로운 전파정류 회로 설계)

  • Bae Sung-Hoon;Lim Shin-Il
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • 제43권4호
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    • pp.53-59
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    • 2006
  • This paper describes the new design technique of full wave rectifier (FWR) for precise measurement instrument and the chip implementation of this FWR circuit with measurement results. Conventional circuits have some problems of complex design and limited output range( $VDD/2{\sim}VLIIV1IT+$). Proposed FWR circuit was simply designed with two 2x1 MUXs, one high speed comparator, and one differential difference amplifier(DDA). One rail-to-rail differential difference amplifier(DDA) performs the DC level shifting to VSS and 2X amplification simultaneously, and enables the full range ($Vss{\sim}VDD$) operation. The proposed FWR circuits shows more than 50% reduction of chip area and power consumption compared to conventional one. Proposed circuit was implemented with 0.35um 1-poly 2-metal CMOS process. Core size is $150um{\times}450um$ and power dissipation is 840uW with 3.3V single supply.

A fast block-matching algorithm using the slice-competition method (슬라이스 경쟁 방식을 이용한 고속 블럭 정합 알고리즘)

  • Jeong, Yeong-Hun;Kim, Jae-Ho
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • 제38권6호
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    • pp.692-702
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    • 2001
  • In this paper, a new block-matching algorithm for standard video encoder is proposed. The algorithm finds a motion vector using the increasing SAD transition curve for each predefined candidates, not a coarse-to-fine approach as a conventional method. To remove low-probability candidates at the early stage of accumulation, a dispersed accumulation matrix is also proposed. This matrix guarantees high-linearity to the SAD transition curve. Therefore, base on this method, we present a new fast block-matching algorithm with the slice competition technique. The Candidate Selection Step and the Candidate Competition Step makes an out-performance model that considerably reduces computational power and not to be trapped into local minima. The computational power is reduced by 10%~70% than that of the conventional BMAs. Regarding computational time, an 18%~35% reduction was achieved by the proposed algorithm. Finally, the average MAD is always low in various bit-streams. The results were also very similar to the MAD of the full search block-matching algorithm.

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A Study on Development of a New Algorithm to Solve Load Flow for Distribution Systems (배전계통조류계산을 위한 새로운 알고리즘에 관한 연구)

  • Moon, Young-Hyun;Yoo, Sung-Young;Choi, Byoung-Kon;Ha, Bock-Nam;Lee, Joong-Ho
    • Proceedings of the KIEE Conference
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    • 대한전기학회 1998년도 하계학술대회 논문집 C
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    • pp.918-922
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    • 1998
  • With the development of industry, the qualitical advancement of power is needed. Since it is placed in the end step of power system, the fault at the distribution system causes some users blackout directly. So if the fault occurs, quick restoration is very important subject and, for the reason, induction of the distribution automation system is now being progressed briskly. For the quick restoration of the faulted distribution system, the load shedding of the blackout-area must be followed, and the other problems like the shedded load, faulted voltage and the rest may cause other accident. Accordingly load shedding must be based on the precise calculation technique during the distribution system load flow(dist flow) calculation. In these days because of its superior convergence characteristic the Newton-Raphson method is most widely used. The number of buses in the distribution system amounts to thousands, and if the fault occurs at the distribution system, the speed for the dist flow calculation is to be improved to apply to the On-Line system. However, Newton-Raphson method takes much time relatively because it must calculate the Jacobian matrix and inverse matrix at every iteration, and in the case of huge load, the equation is hard to converge. In this thesis. matrix equation is used to make algebraical expression and then to solve load flow equation and to modify above defects. Then the complex matrix is divided into real part and imaginary part to keep sparcity. As a result time needed for calculation diminished. Application of mentioned algorithm to 302 bus, 700 bus, 1004 bus system led to almost identical result got by Newton-Raphson method and showed constant convergence characteristic. The effect of time reduction showed 88.2%, 86.4%, 85.1% at each case of 302 bus, 700 bus system 86.4%, and 1004 bus system.

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Trends of Underground $CO_2$ Storage Technology for the Large Scale Reduction of GHG (온실가스 대량감축을 위한 $CO_2$ 지중저장의 기술 동향)

  • Chae, Kwagn-Seok;Lee, Sang-Pil;Yoon, Sung-Wook;Matsuoka, Toshifumi
    • Tunnel and Underground Space
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    • 제20권5호
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    • pp.309-317
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    • 2010
  • CCS (Carbon dioxide Capture and Storage) is a means of mitigating the contribution of $CO_2$ to the Greenhouse gas, from large point sources such as power plants and steel companies. CCS is a process whereby $CO_2$ is captured from gases produced by fossil fuel combustion, compressed, transported and injected into deep geologic formations for permanent storage. CCS applied to a conventional power plant can reduce $CO_2$ emissions to the atmosphere by approximately 80~90% compared to a plant without CCS. The IPCC estimates that the economic potential of CCS will be between 10% and 55% of the total carbon mitigation effort by year 2100. In this paper, overseas sites where CCS technology is being applied and technical development trends for CCS are briefly reviewed.

Bending analysis of porous microbeams based on the modified strain gradient theory including stretching effect

  • Lemya Hanifi Hachemi Amar;Abdelhakim Kaci;Aicha Bessaim;Mohammed Sid Ahmed Houari;Abdelouahed Tounsi
    • Structural Engineering and Mechanics
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    • 제89권3호
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    • pp.225-238
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    • 2024
  • In this paper, a quasi-3D hyperbolic shear deformation theory for the bending responses of a functionally graded (FG) porous micro-beam is based on a modified couple stress theory requiring only one material length scale parameter that can capture the size influence. The model proposed accounts for both shear and normal deformation effects through an illustrative variation of all displacements across the thickness and satisfies the zero traction boundary conditions on the top and bottom surfaces of the micro-beam. The effective material properties of the functionally graded micro-beam are assumed to vary in the thickness direction and are estimated using the homogenization method of power law distribution, which is modified to approximate the porous material properties with even and uneven distributions of porosity phases. The equilibrium equations are obtained using the virtual work principle and solved using Navier's technique. The validity of the derived formulation is established by comparing it with the ones available in the literature. Numerical examples are presented to investigate the influences of the power law index, material length scale parameter, beam thickness, and shear and normal deformation effects on the mechanical characteristics of the FG micro-beam. The results demonstrate that the inclusion of the size effects increases the microbeams stiffness, which consequently leads to a reduction in deflections. In contrast, the shear and normal deformation effects are just the opposite.