• 전기전자학회논문지
• /
• 제16권2호
• /
• pp.102-108
• /
• 2012

3D-IC는 2D-IC와 비교하여 전력 공급 네트워크 설계 시에 더 큰 공급 전류와 더 많은 전력 공급 경로들 때문에 몇 가지 문제점을 가지고 있다. 전력 공급 네트워크는 전력 범프와 전력 TSV로 구성되고, 각 노드의 전압 강하는 전력 범프와 전력 TSV의 개수와 위치에 따라 다양한 값을 가지게 된다. 그래서 칩이 정상적으로 동작하기 위해서는 전압 강하 조건을 만족시키면서 전력 범프와 전력 TSV를 최적화하는 것이 중요하다. 본 논문에서는 3D-IC 전력 공급 네트워크에서 최적의 전력 메시 구조를 통한 전력 범프와 전력 TSV 최적화를 제안한다.

• ETRI Journal
• /
• 제36권4호
• /
• pp.643-653
• /
• 2014

To reduce interconnect delay and power consumption while improving chip performance, a three-dimensional integrated circuit (3D IC) has been developed with die-stacking and through-silicon via (TSV) techniques. The power supply problem is one of the essential challenges in 3D IC design because IR-drop caused by insufficient supply voltage in a 3D chip reduces the chip performance. In particular, power bumps and TSVs are placed to minimize IR-drop in a 3D power delivery network. In this paper, we propose a design methodology for 3D power delivery networks to minimize the number of power bumps and TSVs with optimum mesh structure and distribute voltage variation more uniformly by shifting the locations of power bumps and TSVs while satisfying IR-drop constraint. Simulation results show that our method can reduce the voltage variation by 29.7% on average while reducing the number of power bumps and TSVs by 76.2% and 15.4%, respectively.

• IEIE Transactions on Smart Processing and Computing
• /
• 제5권5호
• /
• pp.349-357
• /
• 2016

The era of the Internet of Things (IoT) is upon us. In this era, minimizing power consumption becomes a primary concern for system-on-chip designers. While traditional power minimization and dynamic power management (DPM) techniques have been heavily explored to improve the power efficiency of devices inside very large-scale integration (VLSI) platforms, there is one critical factor that is often overlooked, which is the power conversion efficiency of a power delivery network (PDN). This paper is a tutorial that focuses on the power conversion efficiency of the PDN, and introduces novel methods to improve it. Circuit-, architecture-, and system-level approaches are presented to optimize PDN designs, while case studies for three different VSLI platforms validate the efficacy of the introduced approaches.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2007년도 제38회 하계학술대회
• /
• pp.75-76
• /
• 2007

Several kinds of High Temperature Superconducting(HTS) power cables have already been developed and evaluated for use in the utility power network. HTS power cable is expected to be used as a very powerful energy delivery system supplying electric power for densely populated cities in the near future, because HTS power cable is capable of the high current density delivery with low AC loss and the size effect comparing with the conventional cable whose capacity is same. Before applying the HTS power cable to real utility network system analysis should be carried out by some simulation tools. Hereby the electrical power system analysis is very important for the practical use of HTS power devices. In this paper, authors propose a real-time simulation method which incorporates a real HTS tapes into the simulated 22.9kV utility power network system using Real Time Digital Simulator(RTDS). For the simulation analysis, a test sample of HTS tapes was actually manufactured, and the transient phenomenon of HTS power cable system was analyzed in the simulated utility power network.

• 마이크로전자및패키징학회지
• /
• 제20권4호
• /
• pp.69-74
• /
• 2013

In this paper, the impact of integrating large number of I/O (Input-Output) and Core power Delivery Network (PDN) on a 6 layers Flip-Chip Ball Grid Array (FCBGA) package is investigated. The impact of core induced supply noise on high-speed I/O interfaces, and high-speed I/O interface's supply noise coupling to adjacent high-speed I/O interfaces' jitter impact are studied. Concurrent stress validation software is used to induce SSO noise on each individual I/O interfaces; and at the same time; periodic noise is introduced from Core PDN into the I/O PDN domain. In order to have the maximum coupling impact, a prototype package is designed to merge the I/O and Core PDN as one while impact on jitter on each I/O interfaces are investigated. In order to understand the impact of the Core to I/O and I/O to I/O noise, the on-die noise measurements were measured and results were compared with the original PDN where each I/O and Core PDN are standalone and isolated are used as a benchmark.

• 한국정보과학회논문지:컴퓨팅의 실제 및 레터
• /
• 제16권4호
• /
• pp.377-382
• /
• 2010

블로그 내에는 다수의 사용자들에게 컨텐츠를 파급시키는 영향력 있는 사용자들이 존재한다. 본 논문에서는 이러한 사용자들을 파급 파워 유저라고 정의하고, 이러한 사용자들을 파악하는 방법에 대하여 논의한다. 본 논문에서는 블로그 연결망에서 파급 파워 유저를 파악하기 위해서 독립 전파 모델을 이용하는데, 독립 전파 모델의 수행을 위해서는 사용자들 간의 동화확률로서 실질적인 값을 부여하는 것이 필수적이다. 따라서 본 논문에서는 사용자의 재생산 파워의 개념과 이를 계량화하는 방법을 제안하고, 사용자의 컨텐츠 파워와 재생산 파워를 이용하여 사용자 간의 동화확률을 부여하는 방안을 제안한다. 끝으로, 실제 블로그 연결망에서 제안하는 기법과 기존의 기법을 이용하여 파워 유저들을 파악하는 실험을 수행하고, 결과를 비교 및 분석한다.

• Journal of Communications and Networks
• /
• 제18권3호
• /
• pp.327-332
• /
• 2016

The routing protocol for low-power and lossy networks (RPL) is an internet protocol based routing protocol developed and standardized by IETF in 2012 to support a wide range of applications for low-power and lossy-networks (LLNs). In LLNs consisting of resource-constrained devices, the energy consumption of battery powered sensing devices during network operations can greatly impact network lifetime. In the case of inefficient route selection, the energy depletion from even a few nodes in the network can damage network integrity and reliability by creating holes in the network. In this paper, a composite energy-aware node metric ($RER_{BDI}$) is proposed for RPL; this metric uses both the residual energy ratio (RER) of the nodes and their battery discharge index. This composite metric helps avoid overburdening power depleted network nodes during packet routing from the source towards the destination oriented directed acyclic graph root node. Additionally, an objective function is defined for RPL, which combines the node metric $RER_{BDI}$ and the expected transmission count (ETX) link quality metric; this helps to improve the overall network packet delivery ratio. The COOJA simulator is used to evaluate the performance of the proposed scheme. The simulations show encouraging results for the proposed scheme in terms of network lifetime, packet delivery ratio and energy consumption, when compared to the most popular schemes for RPL like ETX, hop-count and RER.

• Journal of Power Electronics
• /
• 제10권3호
• /
• pp.320-327
• /
• 2010

In this paper, multiple offshore wave energy converters with different output characteristics are connected to one power distribution substation. The connection between the power take-off of the different wave energy converters and the electrical power transmission system is presented in order to investigate whether multiple wave energy converters can augment energy yield and improve network integration capabilities. Moreover, the model of an array of wave energy converters is developed with the goal of analyzing the effects of the offshore wave farm on the electrical network to which it is connected. It is also developed to ensure that the electricity generated by the array is sufficiently controllable, and of a quality that can be integrate into the electricity supply network without unduly increasing the cost of connection, production or delivery.

• Journal of electromagnetic engineering and science
• /
• 제13권4호
• /
• pp.233-239
• /
• 2013

This paper proposes an accurate approach for predicting transferred power from a noise source to integrated circuits based on the characteristics of the power transfer network. A power delivery trace on a package and a printed circuit board are designed to transmit power from an external source to integrated circuits. The power is demonstrated between an injection terminal on the edge of the printed circuit board and integrated circuits, and the power transfer function of the power distribution network is derived. A two-tier calibration is applied to the test, and scattering parameters of the network are measured for the calculation of the power transfer function. After testing to obtain the indispensable parameters, the real received and tolerable power of the integrated circuits can be easily achieved. Our proposed estimation method is an enhancement of the existing the International Electrotechnical Commission standard for precise prediction of the electromagnetic immunity of integrated circuits.

• 스마트미디어저널
• /
• 제13권1호
• /
• pp.45-51
• /
• 2024

Long Range Wide Area Network (LoRaWAN) is a widely adopted Internet of Things (IoT) protocol due to its high range and lower energy consumption. LoRaWAN utilizes Adaptive Data Rate (ADR) for efficient resource (e.g., spreading factor and transmission power) management. The ADR manages these two resource parameters on the network server side and end device side. This paper focuses on analyzing the ADR and Gaussian ADR performance of LoRaWAN. We have performed NS3 simulation under a static scenario by varying the antenna height. The simulation results showed that antenna height has a significant impact on the packet delivery ratio. Higher antenna height (e.g., 50 m) has shown an improved packet success ratio when compared with lower antenna height (e.g., 10 m) in static and mobility scenarios. Based on the results, it is suggested to use the antenna at higher allevation for successful packet delivery.